From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3GB-000659-Bx for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3G1-0004LE-Jd for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:23 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:64951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3G1-0004KB-DE for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:13 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so5672387pad.4 for ; Tue, 16 Oct 2012 02:16:11 -0700 (PDT) From: Peter Crosthwaite Date: Tue, 16 Oct 2012 19:15:50 +1000 Message-Id: <1350378950-10614-1-git-send-email-peter.crosthwaite@xilinx.com> Subject: [Qemu-devel] [PATCH] target-arm/translate: Fix RRX operands List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Peter Crosthwaite Instructions that both use the RRX second operand and update CS were incorrect, as the Carry flag was updated too early. An example of such an instruction would be: ands r12,r13,RRX Ands, because of the "s" flag will update the carry flag. But the RRX second operand rotates through the C flag which should happen before the update. Fixed the ordering of the two, the old carry is read by "r13,RRX" before being updated. Signed-off-by: Peter Crosthwaite Reported-by: Vinesh Peringat --- target-arm/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index c6840b7..daccb15 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -516,10 +516,10 @@ static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) tcg_gen_rotri_i32(var, var, shift); break; } else { TCGv tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_CF, 31); if (flags) shifter_out_im(var, 0); tcg_gen_shri_i32(var, var, 1); - tcg_gen_shli_i32(tmp, cpu_CF, 31); tcg_gen_or_i32(var, var, tmp); tcg_temp_free_i32(tmp); } -- 1.7.0.4