From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WC-0003V9-FD for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3W4-0000sG-Ob for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:32:56 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:48469) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3W4-0000rm-I2 for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:32:48 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so3065165dad.4 for ; Tue, 16 Oct 2012 02:32:47 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 16 Oct 2012 19:32:12 +1000 Message-Id: <1350379951-17615-2-git-send-email-rth@twiddle.net> In-Reply-To: <1350379951-17615-1-git-send-email-rth@twiddle.net> References: <1350379951-17615-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com Infrastructure to be used to clean up handling of temporaries. Signed-off-by: Richard Henderson --- target-sparc/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6cef96b..eec0db0 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -83,7 +83,9 @@ typedef struct DisasContext { struct TranslationBlock *tb; sparc_def_t *def; TCGv_i32 t32[3]; + TCGv ttl[5]; int n_t32; + int n_ttl; } DisasContext; typedef struct { @@ -263,6 +265,49 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr) #endif } +static inline TCGv get_temp_tl(DisasContext *dc) +{ + TCGv t; + assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); + dc->ttl[dc->n_ttl++] = t = tcg_temp_new(); + return t; +} + +static inline TCGv gen_load_gpr(DisasContext *dc, int reg) +{ + if (reg == 0 || reg >= 8) { + TCGv t = get_temp_tl(dc); + if (reg == 0) { + tcg_gen_movi_tl(t, 0); + } else { + tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); + } + return t; + } else { + return cpu_gregs[reg]; + } +} + +static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v) +{ + if (reg > 0) { + if (reg < 8) { + tcg_gen_mov_tl(cpu_gregs[reg], v); + } else { + tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); + } + } +} + +static inline TCGv gen_dest_gpr(DisasContext *dc, int reg) +{ + if (reg == 0 || reg >= 8) { + return get_temp_tl(dc); + } else { + return cpu_gregs[reg]; + } +} + static inline void gen_movl_reg_TN(int reg, TCGv tn) { if (reg == 0) @@ -5229,6 +5274,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } dc->n_t32 = 0; } + if (dc->n_ttl != 0) { + int i; + for (i = dc->n_ttl - 1; i >= 0; --i) { + tcg_temp_free(dc->ttl[i]); + } + dc->n_ttl = 0; + } } static inline void gen_intermediate_code_internal(TranslationBlock * tb, -- 1.7.11.7