From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55045) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOtrt-0002OB-MT for qemu-devel@nongnu.org; Thu, 18 Oct 2012 13:26:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TOtrs-0002aF-2Y for qemu-devel@nongnu.org; Thu, 18 Oct 2012 13:26:49 -0400 Received: from 38.0.169.217.in-addr.arpa ([217.169.0.38]:32886 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOtrr-0002ZW-SL for qemu-devel@nongnu.org; Thu, 18 Oct 2012 13:26:47 -0400 From: Peter Maydell Date: Thu, 18 Oct 2012 18:26:42 +0100 Message-Id: <1350581204-24456-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 0/2] target-arm: inline abs, 64-bit negate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org Two minor patches which inline some operations rather than using helper functions. The 64 bit negate is a no-brainer since there's a simple TCG op for it. For abs we implement in terms of movcond: movi_i32 tmp6,$0x0 neg_i32 tmp7,tmp5 movcond_i32 tmp5,tmp5,tmp6,tmp5,tmp7,gt which the x86-64 backend turns into: 0x603b53a7: mov %ebp,%ebx 0x603b53a9: neg %ebx 0x603b53ab: mov %ebp,%r12d 0x603b53ae: test %ebp,%ebp 0x603b53b0: cmovle %ebx,%r12d Not sure why it felt the need to use an extra move there, but for ARM this isn't in a particularly performance critical bit of the instruction set (it's a Neon operation) so I'm not too worried. (A fully native TCG abs op would be able to use the fact that neg sets flags to avoid the test as well.) Peter Maydell (2): target-arm: Use TCG operation for Neon 64 bit negation target-arm: Implement abs_i32 inline rather than as a helper target-arm/helper.c | 5 ----- target-arm/helper.h | 2 -- target-arm/neon_helper.c | 6 ------ target-arm/translate.c | 14 +++++++++++--- 4 files changed, 11 insertions(+), 16 deletions(-) -- 1.7.9.5