From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33026) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPcr5-0004sD-OV for qemu-devel@nongnu.org; Sat, 20 Oct 2012 13:29:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPcr4-0007Kt-My for qemu-devel@nongnu.org; Sat, 20 Oct 2012 13:28:59 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45769) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPcr4-0007Jw-Gu for qemu-devel@nongnu.org; Sat, 20 Oct 2012 13:28:58 -0400 From: Aurelien Jarno Date: Sat, 20 Oct 2012 19:28:51 +0200 Message-Id: <1350754131-18667-2-git-send-email-aurelien@aurel32.net> In-Reply-To: <1350754131-18667-1-git-send-email-aurelien@aurel32.net> References: <1350754131-18667-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 2/2] tcg/i386: remove ld/st third argument register constraint List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno On x86_64, remove the constraint on the third argument register which is not needed: - For loads the helper arguments are env, addr, mem_idx. The addr value should not be in the two first argument registers as they are used in tcg_out_tlb_load(). - For stores the helper arguments are env, addr, data, mem_idx. The addr and data values should not be in the two first argument registers as they are used in tcg_out_tlb_load(). The data value should also not be in the two first argument registers, but could be in the third argument register in which case it would be already loaded at the right location. Signed-off-by: Aurelien Jarno --- tcg/i386/tcg-target.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 4c59e33..9c8f69a 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -92,7 +92,6 @@ static const int tcg_target_call_oarg_regs[] = { #if TCG_TARGET_REG_BITS == 64 # define TCG_REG_L0 tcg_target_call_iarg_regs[0] # define TCG_REG_L1 tcg_target_call_iarg_regs[1] -# define TCG_REG_L2 tcg_target_call_iarg_regs[2] #else # define TCG_REG_L0 TCG_REG_EAX # define TCG_REG_L1 TCG_REG_EDX @@ -181,14 +180,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) ct->ct |= TCG_CT_REG; #if TCG_TARGET_REG_BITS == 64 tcg_regset_set32(ct->u.regs, 0, 0xffff); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L2); #else tcg_regset_set32(ct->u.regs, 0, 0xff); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); #endif + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); break; case 'e': -- 1.7.10.4