[Qemu-devel] [PULL 0/4] target-arm queue

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for the current target-arm queue. Some
minor tweaks and the patch which handles get/put_user() failure
in the semihosting code. Please pull.

thanks
-- PMM

The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:

  Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:

  target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)

----------------------------------------------------------------
Peter Maydell (4):
      arm-semi.c: Handle get/put_user() failure accessing arguments
      target-arm: Use TCG operation for Neon 64 bit negation
      target-arm: Implement abs_i32 inline rather than as a helper
      target-arm: Remove out of date FIXME regarding saturating arithmetic

 target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
 target-arm/helper.c      |    5 --
 target-arm/helper.h      |    2 -
 target-arm/neon_helper.c |    6 --
 target-arm/op_helper.c   |    2 -
 target-arm/translate.c   |   15 ++++-
 6 files changed, 118 insertions(+), 79 deletions(-)

[Qemu-devel] [PATCH 1/4] arm-semi.c: Handle get/put_user() failure accessing arguments

[Peter Maydell]

Rework the handling of arguments to ARM semihosting calls so that we
handle a possible failure return from get_user_ual() or put_user_ual().
(This incidentally silences a lot of warnings from clang about
"expression result unused").

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/arm-semi.c |  167 +++++++++++++++++++++++++++++++------------------
 1 file changed, 106 insertions(+), 61 deletions(-)

diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 73bde58..7743d67 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -166,17 +166,20 @@ static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong er
 #endif
 }
 
-#define ARG(n)					\
-({						\
-    target_ulong __arg;				\
-    /* FIXME - handle get_user() failure */	\
-    get_user_ual(__arg, args + (n) * 4);	\
-    __arg;					\
-})
+/* Read the input value from the argument block; fail the semihosting
+ * call if the memory read fails.
+ */
+#define GET_ARG(n) do {                                 \
+    if (get_user_ual(arg ## n, args + (n) * 4)) {       \
+        return (uint32_t)-1;                            \
+    }                                                   \
+} while (0)
+
 #define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
 uint32_t do_arm_semihosting(CPUARMState *env)
 {
     target_ulong args;
+    target_ulong arg0, arg1, arg2, arg3;
     char * s;
     int nr;
     uint32_t ret;
@@ -191,33 +194,39 @@ uint32_t do_arm_semihosting(CPUARMState *env)
     args = env->regs[1];
     switch (nr) {
     case TARGET_SYS_OPEN:
-        if (!(s = lock_user_string(ARG(0))))
+        GET_ARG(0);
+        GET_ARG(1);
+        GET_ARG(2);
+        s = lock_user_string(arg0);
+        if (!s) {
             /* FIXME - should this error code be -TARGET_EFAULT ? */
             return (uint32_t)-1;
-        if (ARG(1) >= 12) {
-            unlock_user(s, ARG(0), 0);
+        }
+        if (arg1 >= 12) {
+            unlock_user(s, arg0, 0);
             return (uint32_t)-1;
         }
         if (strcmp(s, ":tt") == 0) {
-            int result_fileno = ARG(1) < 4 ? STDIN_FILENO : STDOUT_FILENO;
-            unlock_user(s, ARG(0), 0);
+            int result_fileno = arg1 < 4 ? STDIN_FILENO : STDOUT_FILENO;
+            unlock_user(s, arg0, 0);
             return result_fileno;
         }
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "open,%s,%x,1a4", ARG(0),
-			   (int)ARG(2)+1, gdb_open_modeflags[ARG(1)]);
+            gdb_do_syscall(arm_semi_cb, "open,%s,%x,1a4", arg0,
+                           (int)arg2+1, gdb_open_modeflags[arg1]);
             ret = env->regs[0];
         } else {
-            ret = set_swi_errno(ts, open(s, open_modeflags[ARG(1)], 0644));
+            ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644));
         }
-        unlock_user(s, ARG(0), 0);
+        unlock_user(s, arg0, 0);
         return ret;
     case TARGET_SYS_CLOSE:
+        GET_ARG(0);
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "close,%x", ARG(0));
+            gdb_do_syscall(arm_semi_cb, "close,%x", arg0);
             return env->regs[0];
         } else {
-            return set_swi_errno(ts, close(ARG(0)));
+            return set_swi_errno(ts, close(arg0));
         }
     case TARGET_SYS_WRITEC:
         {
@@ -248,35 +257,45 @@ uint32_t do_arm_semihosting(CPUARMState *env)
         unlock_user(s, args, 0);
         return ret;
     case TARGET_SYS_WRITE:
-        len = ARG(2);
+        GET_ARG(0);
+        GET_ARG(1);
+        GET_ARG(2);
+        len = arg2;
         if (use_gdb_syscalls()) {
             arm_semi_syscall_len = len;
-            gdb_do_syscall(arm_semi_cb, "write,%x,%x,%x", ARG(0), ARG(1), len);
+            gdb_do_syscall(arm_semi_cb, "write,%x,%x,%x", arg0, arg1, len);
             return env->regs[0];
         } else {
-            if (!(s = lock_user(VERIFY_READ, ARG(1), len, 1)))
+            s = lock_user(VERIFY_READ, arg1, len, 1);
+            if (!s) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
-            ret = set_swi_errno(ts, write(ARG(0), s, len));
-            unlock_user(s, ARG(1), 0);
+            }
+            ret = set_swi_errno(ts, write(arg0, s, len));
+            unlock_user(s, arg1, 0);
             if (ret == (uint32_t)-1)
                 return -1;
             return len - ret;
         }
     case TARGET_SYS_READ:
-        len = ARG(2);
+        GET_ARG(0);
+        GET_ARG(1);
+        GET_ARG(2);
+        len = arg2;
         if (use_gdb_syscalls()) {
             arm_semi_syscall_len = len;
-            gdb_do_syscall(arm_semi_cb, "read,%x,%x,%x", ARG(0), ARG(1), len);
+            gdb_do_syscall(arm_semi_cb, "read,%x,%x,%x", arg0, arg1, len);
             return env->regs[0];
         } else {
-            if (!(s = lock_user(VERIFY_WRITE, ARG(1), len, 0)))
+            s = lock_user(VERIFY_WRITE, arg1, len, 0);
+            if (!s) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
-            do
-              ret = set_swi_errno(ts, read(ARG(0), s, len));
-            while (ret == -1 && errno == EINTR);
-            unlock_user(s, ARG(1), len);
+            }
+            do {
+                ret = set_swi_errno(ts, read(arg0, s, len));
+            } while (ret == -1 && errno == EINTR);
+            unlock_user(s, arg1, len);
             if (ret == (uint32_t)-1)
                 return -1;
             return len - ret;
@@ -285,30 +304,34 @@ uint32_t do_arm_semihosting(CPUARMState *env)
        /* XXX: Read from debug console. Not implemented.  */
         return 0;
     case TARGET_SYS_ISTTY:
+        GET_ARG(0);
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "isatty,%x", ARG(0));
+            gdb_do_syscall(arm_semi_cb, "isatty,%x", arg0);
             return env->regs[0];
         } else {
-            return isatty(ARG(0));
+            return isatty(arg0);
         }
     case TARGET_SYS_SEEK:
+        GET_ARG(0);
+        GET_ARG(1);
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "lseek,%x,%x,0", ARG(0), ARG(1));
+            gdb_do_syscall(arm_semi_cb, "lseek,%x,%x,0", arg0, arg1);
             return env->regs[0];
         } else {
-            ret = set_swi_errno(ts, lseek(ARG(0), ARG(1), SEEK_SET));
+            ret = set_swi_errno(ts, lseek(arg0, arg1, SEEK_SET));
             if (ret == (uint32_t)-1)
               return -1;
             return 0;
         }
     case TARGET_SYS_FLEN:
+        GET_ARG(0);
         if (use_gdb_syscalls()) {
             gdb_do_syscall(arm_semi_flen_cb, "fstat,%x,%x",
-			   ARG(0), env->regs[13]-64);
+                           arg0, env->regs[13]-64);
             return env->regs[0];
         } else {
             struct stat buf;
-            ret = set_swi_errno(ts, fstat(ARG(0), &buf));
+            ret = set_swi_errno(ts, fstat(arg0, &buf));
             if (ret == (uint32_t)-1)
                 return -1;
             return buf.st_size;
@@ -317,35 +340,43 @@ uint32_t do_arm_semihosting(CPUARMState *env)
         /* XXX: Not implemented.  */
         return -1;
     case TARGET_SYS_REMOVE:
+        GET_ARG(0);
+        GET_ARG(1);
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "unlink,%s", ARG(0), (int)ARG(1)+1);
+            gdb_do_syscall(arm_semi_cb, "unlink,%s", arg0, (int)arg1+1);
             ret = env->regs[0];
         } else {
-            if (!(s = lock_user_string(ARG(0))))
+            s = lock_user_string(arg0);
+            if (!s) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
+            }
             ret =  set_swi_errno(ts, remove(s));
-            unlock_user(s, ARG(0), 0);
+            unlock_user(s, arg0, 0);
         }
         return ret;
     case TARGET_SYS_RENAME:
+        GET_ARG(0);
+        GET_ARG(1);
+        GET_ARG(2);
+        GET_ARG(3);
         if (use_gdb_syscalls()) {
             gdb_do_syscall(arm_semi_cb, "rename,%s,%s",
-                           ARG(0), (int)ARG(1)+1, ARG(2), (int)ARG(3)+1);
+                           arg0, (int)arg1+1, arg2, (int)arg3+1);
             return env->regs[0];
         } else {
             char *s2;
-            s = lock_user_string(ARG(0));
-            s2 = lock_user_string(ARG(2));
+            s = lock_user_string(arg0);
+            s2 = lock_user_string(arg2);
             if (!s || !s2)
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 ret = (uint32_t)-1;
             else
                 ret = set_swi_errno(ts, rename(s, s2));
             if (s2)
-                unlock_user(s2, ARG(2), 0);
+                unlock_user(s2, arg2, 0);
             if (s)
-                unlock_user(s, ARG(0), 0);
+                unlock_user(s, arg0, 0);
             return ret;
         }
     case TARGET_SYS_CLOCK:
@@ -353,15 +384,19 @@ uint32_t do_arm_semihosting(CPUARMState *env)
     case TARGET_SYS_TIME:
         return set_swi_errno(ts, time(NULL));
     case TARGET_SYS_SYSTEM:
+        GET_ARG(0);
+        GET_ARG(1);
         if (use_gdb_syscalls()) {
-            gdb_do_syscall(arm_semi_cb, "system,%s", ARG(0), (int)ARG(1)+1);
+            gdb_do_syscall(arm_semi_cb, "system,%s", arg0, (int)arg1+1);
             return env->regs[0];
         } else {
-            if (!(s = lock_user_string(ARG(0))))
+            s = lock_user_string(arg0);
+            if (!s) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
+            }
             ret = set_swi_errno(ts, system(s));
-            unlock_user(s, ARG(0), 0);
+            unlock_user(s, arg0, 0);
             return ret;
         }
     case TARGET_SYS_ERRNO:
@@ -375,22 +410,24 @@ uint32_t do_arm_semihosting(CPUARMState *env)
             /* Build a command-line from the original argv.
              *
              * The inputs are:
-             *     * ARG(0), pointer to a buffer of at least the size
-             *               specified in ARG(1).
-             *     * ARG(1), size of the buffer pointed to by ARG(0) in
+             *     * arg0, pointer to a buffer of at least the size
+             *               specified in arg1.
+             *     * arg1, size of the buffer pointed to by arg0 in
              *               bytes.
              *
              * The outputs are:
-             *     * ARG(0), pointer to null-terminated string of the
+             *     * arg0, pointer to null-terminated string of the
              *               command line.
-             *     * ARG(1), length of the string pointed to by ARG(0).
+             *     * arg1, length of the string pointed to by arg0.
              */
 
             char *output_buffer;
-            size_t input_size = ARG(1);
+            size_t input_size;
             size_t output_size;
             int status = 0;
-
+            GET_ARG(0);
+            GET_ARG(1);
+            input_size = arg1;
             /* Compute the size of the output string.  */
 #if !defined(CONFIG_USER_ONLY)
             output_size = strlen(ts->boot_info->kernel_filename)
@@ -414,10 +451,13 @@ uint32_t do_arm_semihosting(CPUARMState *env)
             }
 
             /* Adjust the command-line length.  */
-            SET_ARG(1, output_size - 1);
+            if (SET_ARG(1, output_size - 1)) {
+                /* Couldn't write back to argument block */
+                return -1;
+            }
 
             /* Lock the buffer on the ARM side.  */
-            output_buffer = lock_user(VERIFY_WRITE, ARG(0), output_size, 0);
+            output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0);
             if (!output_buffer) {
                 return -1;
             }
@@ -449,7 +489,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
         out:
 #endif
             /* Unlock the buffer on the ARM side.  */
-            unlock_user(output_buffer, ARG(0), output_size);
+            unlock_user(output_buffer, arg0, output_size);
 
             return status;
         }
@@ -457,6 +497,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
         {
             uint32_t *ptr;
             uint32_t limit;
+            GET_ARG(0);
 
 #ifdef CONFIG_USER_ONLY
             /* Some C libraries assume the heap immediately follows .bss, so
@@ -477,25 +518,29 @@ uint32_t do_arm_semihosting(CPUARMState *env)
                 ts->heap_limit = limit;
             }
 
-            if (!(ptr = lock_user(VERIFY_WRITE, ARG(0), 16, 0)))
+            ptr = lock_user(VERIFY_WRITE, arg0, 16, 0);
+            if (!ptr) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
+            }
             ptr[0] = tswap32(ts->heap_base);
             ptr[1] = tswap32(ts->heap_limit);
             ptr[2] = tswap32(ts->stack_base);
             ptr[3] = tswap32(0); /* Stack limit.  */
-            unlock_user(ptr, ARG(0), 16);
+            unlock_user(ptr, arg0, 16);
 #else
             limit = ram_size;
-            if (!(ptr = lock_user(VERIFY_WRITE, ARG(0), 16, 0)))
+            ptr = lock_user(VERIFY_WRITE, arg0, 16, 0);
+            if (!ptr) {
                 /* FIXME - should this error code be -TARGET_EFAULT ? */
                 return (uint32_t)-1;
+            }
             /* TODO: Make this use the limit of the loaded application.  */
             ptr[0] = tswap32(limit / 2);
             ptr[1] = tswap32(limit);
             ptr[2] = tswap32(limit); /* Stack base */
             ptr[3] = tswap32(0); /* Stack limit.  */
-            unlock_user(ptr, ARG(0), 16);
+            unlock_user(ptr, arg0, 16);
 #endif
             return 0;
         }
-- 
1.7.9.5

[Qemu-devel] [PATCH 2/4] target-arm: Use TCG operation for Neon 64 bit negation

[Peter Maydell]

Use the TCG operation to do Neon 64 bit negations rather than calling
a helper routine for it.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.h      |    1 -
 target-arm/neon_helper.c |    6 ------
 target-arm/translate.c   |    4 +++-
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/target-arm/helper.h b/target-arm/helper.h
index 8b9adf1..fa3472f 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -339,7 +339,6 @@ DEF_HELPER_2(neon_mull_s16, i64, i32, i32)
 
 DEF_HELPER_1(neon_negl_u16, i64, i64)
 DEF_HELPER_1(neon_negl_u32, i64, i64)
-DEF_HELPER_1(neon_negl_u64, i64, i64)
 
 DEF_HELPER_2(neon_qabs_s8, i32, env, i32)
 DEF_HELPER_2(neon_qabs_s16, i32, env, i32)
diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index 9aa920d..89280b6 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -1664,12 +1664,6 @@ uint64_t HELPER(neon_negl_u32)(uint64_t x)
     return low | ((uint64_t)high << 32);
 }
 
-/* FIXME:  There should be a native op for this.  */
-uint64_t HELPER(neon_negl_u64)(uint64_t x)
-{
-    return -x;
-}
-
 /* Saturating sign manipulation.  */
 /* ??? Make these use NEON_VOP1 */
 #define DO_QABS8(x) do { \
diff --git a/target-arm/translate.c b/target-arm/translate.c
index daccb15..d33f94c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4184,7 +4184,9 @@ static inline void gen_neon_negl(TCGv_i64 var, int size)
     switch (size) {
     case 0: gen_helper_neon_negl_u16(var, var); break;
     case 1: gen_helper_neon_negl_u32(var, var); break;
-    case 2: gen_helper_neon_negl_u64(var, var); break;
+    case 2:
+        tcg_gen_neg_i64(var, var);
+        break;
     default: abort();
     }
 }
-- 
1.7.9.5

[Qemu-devel] [PATCH 3/4] target-arm: Implement abs_i32 inline rather than as a helper

[Peter Maydell]

Implement abs_i32 inline (with movcond) rather than using a helper
function.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c    |    5 -----
 target-arm/helper.h    |    1 -
 target-arm/translate.c |   11 +++++++++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8f2cba6..ab8b734 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1562,11 +1562,6 @@ uint32_t HELPER(rbit)(uint32_t x)
     return x;
 }
 
-uint32_t HELPER(abs)(uint32_t x)
-{
-    return ((int32_t)x < 0) ? -x : x;
-}
-
 #if defined(CONFIG_USER_ONLY)
 
 void do_interrupt (CPUARMState *env)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index fa3472f..60812de 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -13,7 +13,6 @@ DEF_HELPER_2(double_saturate, i32, env, s32)
 DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_CONST | TCG_CALL_PURE, s32, s32, s32)
 DEF_HELPER_FLAGS_2(udiv, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
 DEF_HELPER_FLAGS_1(rbit, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
-DEF_HELPER_FLAGS_1(abs, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
 
 #define PAS_OP(pfx)  \
     DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \
diff --git a/target-arm/translate.c b/target-arm/translate.c
index d33f94c..25433da 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -462,8 +462,15 @@ static void gen_sar(TCGv dest, TCGv t0, TCGv t1)
     tcg_temp_free_i32(tmp1);
 }
 
-/* FIXME:  Implement this natively.  */
-#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
+static void tcg_gen_abs_i32(TCGv dest, TCGv src)
+{
+    TCGv c0 = tcg_const_i32(0);
+    TCGv tmp = tcg_temp_new_i32();
+    tcg_gen_neg_i32(tmp, src);
+    tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp);
+    tcg_temp_free_i32(c0);
+    tcg_temp_free_i32(tmp);
+}
 
 static void shifter_out_im(TCGv var, int shift)
 {
-- 
1.7.9.5

[Qemu-devel] [PATCH 4/4] target-arm: Remove out of date FIXME regarding saturating arithmetic

[Peter Maydell]

Remove an out of date FIXME regarding the saturating arithmetic helpers:
we now do pass a pointer to CPUARMState to these helpers, and since
the AREG0 changes went in there is no difference between helper.c
and op_helper.c and therefore no point in moving the functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/op_helper.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index aef592a..6e3ab90 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -93,8 +93,6 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
 }
 #endif
 
-/* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
-   instructions into helper.c  */
 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 {
     uint32_t res = a + b;
-- 
1.7.9.5

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

On Wed, Oct 24, 2012 at 1:02 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for the current target-arm queue. Some
> minor tweaks and the patch which handles get/put_user() failure
> in the semihosting code. Please pull.

Thanks, pulled.

>
> thanks
> -- PMM
>
> The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:
>
>   Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:
>
>   target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)
>
> ----------------------------------------------------------------
> Peter Maydell (4):
>       arm-semi.c: Handle get/put_user() failure accessing arguments
>       target-arm: Use TCG operation for Neon 64 bit negation
>       target-arm: Implement abs_i32 inline rather than as a helper
>       target-arm: Remove out of date FIXME regarding saturating arithmetic
>
>  target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
>  target-arm/helper.c      |    5 --
>  target-arm/helper.h      |    2 -
>  target-arm/neon_helper.c |    6 --
>  target-arm/op_helper.c   |    2 -
>  target-arm/translate.c   |   15 ++++-
>  6 files changed, 118 insertions(+), 79 deletions(-)

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

target-arm pullreq, containing a fix for a dumb SRS bug I
introduced, and the update to migration to use vmstate
(both of which have been on the list since before freeze).
Please pull.

thanks
-- PMM

The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:

  configure: remove duplicate test (2013-04-18 14:12:31 +0200)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next

for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:

  target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)

----------------------------------------------------------------
Juan Quintela (1):
      target-arm: port ARM CPU save/load to use VMState

Peter Chubb (1):
      target-arm: Reinsert missing return statement in ARM mode SRS decode

Peter Maydell (2):
      target-arm: Add some missing CPU state fields to VMState
      target-arm: Correctly restore FPSCR

 target-arm/cpu-qom.h   |    4 +
 target-arm/cpu.c       |    1 +
 target-arm/cpu.h       |    2 -
 target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
 target-arm/translate.c |    1 +
 5 files changed, 222 insertions(+), 216 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 3:06 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm pullreq, containing a fix for a dumb SRS bug I
> introduced, and the update to migration to use vmstate
> (both of which have been on the list since before freeze).
> Please pull.
>
> thanks
> -- PMM
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
>
> for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:
>
>   target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)
>
> ----------------------------------------------------------------
> Juan Quintela (1):
>       target-arm: port ARM CPU save/load to use VMState
>
> Peter Chubb (1):
>       target-arm: Reinsert missing return statement in ARM mode SRS decode
>
> Peter Maydell (2):
>       target-arm: Add some missing CPU state fields to VMState
>       target-arm: Correctly restore FPSCR
>
>  target-arm/cpu-qom.h   |    4 +
>  target-arm/cpu.c       |    1 +
>  target-arm/cpu.h       |    2 -
>  target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
>  target-arm/translate.c |    1 +
>  5 files changed, 222 insertions(+), 216 deletions(-)

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A handful of minor ARM bugfixes...

thanks
-- PMM

The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:

  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124

for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:

  target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * fix minimum RAM check warning on xlnx-ep108
 * remove unused define from aarch64-linux-user.mak config
 * don't mask out bits [47:40] in ARMv8 LPAE descriptors
 * correct unallocated instruction checks for ldst_excl

----------------------------------------------------------------
Alistair Francis (1):
      xlnx-ep108: Fix minimum RAM check

Peter Maydell (3):
      default-configs/aarch64-linux-user.mak: Remove unused define
      target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
      target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

 default-configs/aarch64-linux-user.mak |  2 --
 hw/arm/xlnx-ep108.c                    |  2 +-
 target-arm/helper.c                    | 12 +++++++++++-
 target-arm/translate-a64.c             | 15 ++-------------
 4 files changed, 14 insertions(+), 17 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 November 2015 at 14:18, Peter Maydell <peter.maydell@linaro.org> wrote:
> A handful of minor ARM bugfixes...
>
> thanks
> -- PMM
>
> The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:
>
>   Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124
>
> for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:
>
>   target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix minimum RAM check warning on xlnx-ep108
>  * remove unused define from aarch64-linux-user.mak config
>  * don't mask out bits [47:40] in ARMv8 LPAE descriptors
>  * correct unallocated instruction checks for ldst_excl
>
> ----------------------------------------------------------------
> Alistair Francis (1):
>       xlnx-ep108: Fix minimum RAM check
>
> Peter Maydell (3):
>       default-configs/aarch64-linux-user.mak: Remove unused define
>       target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
>       target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; here's the last target-arm pull request before I
go off on holiday -- four fairly minor bug fixes.
Hopefully it merges without problems, because I won't
be around tomorrow to do a respin :-)

thanks
-- PMM

The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:

  Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107

for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:

  hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * bitbang_i2c: Handle NACKs from devices
 * Fix corruption of CPSR when SCTLR.EE is set
 * nvic: set pending status for not active interrupts
 * char: cadence: check baud rate generator and divider values

----------------------------------------------------------------
Julian Brown (1):
      Fix corruption of CPSR when SCTLR.EE is set

Marcin Krzeminski (1):
      nvic: set pending status for not active interrupts

Peter Maydell (1):
      hw/i2c/bitbang_i2c: Handle NACKs from devices

Prasad J Pandit (1):
      char: cadence: check baud rate generator and divider values

 hw/char/cadence_uart.c | 15 +++++++++++++++
 hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
 hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
 target-arm/helper.c    |  2 +-
 4 files changed, 51 insertions(+), 7 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 1865 bytes --]

On Mon, Nov 07, 2016 at 10:47:29AM +0000, Peter Maydell wrote:
> Hi; here's the last target-arm pull request before I
> go off on holiday -- four fairly minor bug fixes.
> Hopefully it merges without problems, because I won't
> be around tomorrow to do a respin :-)
> 
> thanks
> -- PMM
> 
> The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:
> 
>   Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107
> 
> for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:
> 
>   hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)
> 
> ----------------------------------------------------------------
> target-arm queue:
>  * bitbang_i2c: Handle NACKs from devices
>  * Fix corruption of CPSR when SCTLR.EE is set
>  * nvic: set pending status for not active interrupts
>  * char: cadence: check baud rate generator and divider values
> 
> ----------------------------------------------------------------
> Julian Brown (1):
>       Fix corruption of CPSR when SCTLR.EE is set
> 
> Marcin Krzeminski (1):
>       nvic: set pending status for not active interrupts
> 
> Peter Maydell (1):
>       hw/i2c/bitbang_i2c: Handle NACKs from devices
> 
> Prasad J Pandit (1):
>       char: cadence: check baud rate generator and divider values
> 
>  hw/char/cadence_uart.c | 15 +++++++++++++++
>  hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
>  hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
>  target-arm/helper.c    |  2 +-
>  4 files changed, 51 insertions(+), 7 deletions(-)

Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging

Stefan

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 455 bytes --]

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A surprisingly short target-arm queue, but no point in holding
onto these waiting for more code to arrive :-)

thanks
-- PMM

The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711

for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:

  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

----------------------------------------------------------------
Alexander Graf (1):
      ARM: KVM: Enable in-kernel timers with user space gic

Joel Stanley (1):
      aspeed: Register all watchdogs

Krzysztof Kozlowski (1):
      hw/misc: Add Exynos4210 Pseudo Random Number Generator

Peter Maydell (1):
      target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

 hw/misc/Makefile.objs       |   2 +-
 include/hw/arm/aspeed_soc.h |   4 +-
 include/sysemu/kvm.h        |  11 ++
 target/arm/cpu.h            |   3 +
 accel/kvm/kvm-all.c         |   5 +
 accel/stubs/kvm-stub.c      |   5 +
 hw/arm/aspeed_soc.c         |  25 ++--
 hw/arm/exynos4210.c         |   4 +
 hw/intc/arm_gic.c           |   7 ++
 hw/misc/exynos4210_rng.c    | 277 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c         |  13 ++-
 target/arm/kvm.c            |  51 ++++++++
 12 files changed, 394 insertions(+), 13 deletions(-)
 create mode 100644 hw/misc/exynos4210_rng.c

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 11 July 2017 at 11:29, Peter Maydell <peter.maydell@linaro.org> wrote:
> A surprisingly short target-arm queue, but no point in holding
> onto these waiting for more code to arrive :-)
>
> thanks
> -- PMM
>
> The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:
>
>   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711
>
> for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:
>
>   target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * v7M: ignore writes to CONTROL.SPSEL from Thread mode
>  * KVM: Enable in-kernel timers with user space gic
>  * aspeed: Register all watchdogs
>  * hw/misc: Add Exynos4210 Pseudo Random Number Generator
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

ARM queue, mostly bug fixes to go into rc0.
The integratorcp and fsl_imx* changes are migration
compat breakers but that's ok for these boards.

thanks
-- PMM


The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:

  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724

for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:

  integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)

----------------------------------------------------------------
target-arm queue:
 * fix a TCG temporary leak in aarch64 rev16
 * fsl_imx*: migrate the ROM contents
 * integratorcp: don't use vmstate_register_ram_global for flash
 * mps2: Correctly set parent bus for SCC device

----------------------------------------------------------------
Emilio G. Cota (1):
      target/arm: fix TCG temp leak in aarch64 rev16

Peter Maydell (3):
      fsl_imx*: Migrate ROM contents
      mps2: Correctly set parent bus for SCC device
      integratorcp: Don't migrate flash using vmstate_register_ram_global()

 hw/arm/fsl-imx25.c         | 4 ++--
 hw/arm/fsl-imx31.c         | 4 ++--
 hw/arm/fsl-imx6.c          | 4 ++--
 hw/arm/integratorcp.c      | 3 +--
 hw/arm/mps2.c              | 2 +-
 target/arm/translate-a64.c | 1 +
 6 files changed, 9 insertions(+), 9 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 July 2017 at 18:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue, mostly bug fixes to go into rc0.
> The integratorcp and fsl_imx* changes are migration
> compat breakers but that's ok for these boards.
>
> thanks
> -- PMM
>
>
> The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:
>
>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724
>
> for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:
>
>   integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix a TCG temporary leak in aarch64 rev16
>  * fsl_imx*: migrate the ROM contents
>  * integratorcp: don't use vmstate_register_ram_global for flash
>  * mps2: Correctly set parent bus for SCC device
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A last handful of patches before the rc0. These are all bugfixes
so they could equally well go into rc1, but since my pullreq
queue is otherwise empty I might as well push them out. The
FPSCR bugfix is definitely one I'd like in rc0; the rest are
not really user-visible I think.

thanks
-- PMM

The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708

for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:

  target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)

----------------------------------------------------------------
target-arm queue:
 * tests/migration-test: Fix read off end of aarch64_kernel array
 * Fix sve_zcr_len_for_el off-by-one error
 * hw/arm/sbsa-ref: Silence Coverity nit
 * vfp_helper: Call set_fpscr_to_host before updating to FPSCR

----------------------------------------------------------------
Peter Maydell (2):
      tests/migration-test: Fix read off end of aarch64_kernel array
      hw/arm/sbsa-ref: Remove unnecessary check for secure_sysmem == NULL

Philippe Mathieu-Daudé (1):
      target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR

Richard Henderson (1):
      target/arm: Fix sve_zcr_len_for_el

 hw/arm/sbsa-ref.c       |  8 ++------
 target/arm/helper.c     |  4 ++--
 target/arm/vfp_helper.c |  4 ++--
 tests/migration-test.c  | 22 +++++++---------------
 4 files changed, 13 insertions(+), 25 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On Mon, 8 Jul 2019 at 14:22, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> A last handful of patches before the rc0. These are all bugfixes
> so they could equally well go into rc1, but since my pullreq
> queue is otherwise empty I might as well push them out. The
> FPSCR bugfix is definitely one I'd like in rc0; the rest are
> not really user-visible I think.
>
> thanks
> -- PMM
>
> The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:
>
>   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708
>
> for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:
>
>   target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * tests/migration-test: Fix read off end of aarch64_kernel array
>  * Fix sve_zcr_len_for_el off-by-one error
>  * hw/arm/sbsa-ref: Silence Coverity nit
>  * vfp_helper: Call set_fpscr_to_host before updating to FPSCR


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190708132237.7911-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190708132237.7911-1-peter.maydell@linaro.org
Type: series
Subject: [Qemu-devel] [PULL 0/4] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190708132237.7911-1-peter.maydell@linaro.org -> patchew/20190708132237.7911-1-peter.maydell@linaro.org
Switched to a new branch 'test'

=== OUTPUT BEGIN ===
checkpatch.pl: no revisions returned for revlist '1'
=== OUTPUT END ===

Test command exited with code: 255


The full log is available at
http://patchew.org/logs/20190708132237.7911-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com