From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 10/19] target-mips: cleanup load/store operations
Date: Tue, 30 Oct 2012 01:12:03 +0100 [thread overview]
Message-ID: <1351555932-19695-11-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1351555932-19695-1-git-send-email-aurelien@aurel32.net>
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/translate.c | 91 ++++++++++++++++-------------------------------
1 file changed, 31 insertions(+), 60 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 732c65d..4485a81 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1029,35 +1029,6 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64)
#undef gen_ldcmp_fpr64
/* load/store instructions. */
-#define OP_LD(insn,fname) \
-static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
-{ \
- tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
-}
-OP_LD(lb,ld8s);
-OP_LD(lbu,ld8u);
-OP_LD(lh,ld16s);
-OP_LD(lhu,ld16u);
-OP_LD(lw,ld32s);
-#if defined(TARGET_MIPS64)
-OP_LD(lwu,ld32u);
-OP_LD(ld,ld64);
-#endif
-#undef OP_LD
-
-#define OP_ST(insn,fname) \
-static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
-{ \
- tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
-}
-OP_ST(sb,st8);
-OP_ST(sh,st16);
-OP_ST(sw,st32);
-#if defined(TARGET_MIPS64)
-OP_ST(sd,st64);
-#endif
-#undef OP_ST
-
#ifdef CONFIG_USER_ONLY
#define OP_LD_ATOMIC(insn,fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
@@ -1171,12 +1142,12 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- op_ld_lwu(t0, t0, ctx);
+ tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lwu";
break;
case OPC_LD:
- op_ld_ld(t0, t0, ctx);
+ tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "ld";
break;
@@ -1203,7 +1174,7 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LDPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- op_ld_ld(t0, t0, ctx);
+ tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "ldpc";
break;
@@ -1211,32 +1182,32 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LWPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- op_ld_lw(t0, t0, ctx);
+ tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lwpc";
break;
case OPC_LW:
- op_ld_lw(t0, t0, ctx);
+ tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lw";
break;
case OPC_LH:
- op_ld_lh(t0, t0, ctx);
+ tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lh";
break;
case OPC_LHU:
- op_ld_lhu(t0, t0, ctx);
+ tcg_gen_qemu_ld16u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lhu";
break;
case OPC_LB:
- op_ld_lb(t0, t0, ctx);
+ tcg_gen_qemu_ld8s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lb";
break;
case OPC_LBU:
- op_ld_lbu(t0, t0, ctx);
+ tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lbu";
break;
@@ -1280,7 +1251,7 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- op_st_sd(t1, t0, ctx);
+ tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
opn = "sd";
break;
case OPC_SDL:
@@ -1295,15 +1266,15 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
break;
#endif
case OPC_SW:
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
opn = "sw";
break;
case OPC_SH:
- op_st_sh(t1, t0, ctx);
+ tcg_gen_qemu_st16(t1, t0, ctx->mem_idx);
opn = "sh";
break;
case OPC_SB:
- op_st_sb(t1, t0, ctx);
+ tcg_gen_qemu_st8(t1, t0, ctx->mem_idx);
opn = "sb";
break;
case OPC_SWL:
@@ -8778,22 +8749,22 @@ static void gen_mips16_save (DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
}
gen_load_gpr(t0, 29);
@@ -8801,7 +8772,7 @@ static void gen_mips16_save (DisasContext *ctx,
#define DECR_AND_STORE(reg) do { \
tcg_gen_subi_tl(t0, t0, 4); \
gen_load_gpr(t1, reg); \
- op_st_sw(t1, t0, ctx); \
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); \
} while (0)
if (do_ra) {
@@ -8899,10 +8870,10 @@ static void gen_mips16_restore (DisasContext *ctx,
tcg_gen_addi_tl(t0, cpu_gpr[29], framesize);
-#define DECR_AND_LOAD(reg) do { \
- tcg_gen_subi_tl(t0, t0, 4); \
- op_ld_lw(t1, t0, ctx); \
- gen_store_gpr(t1, reg); \
+#define DECR_AND_LOAD(reg) do { \
+ tcg_gen_subi_tl(t0, t0, 4); \
+ tcg_gen_qemu_ld32u(t1, t0, ctx->mem_idx); \
+ gen_store_gpr(t1, reg); \
} while (0)
if (do_ra) {
@@ -10408,7 +10379,7 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0);
}
- op_ld_lw(t1, t0, ctx);
+ tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd);
tcg_temp_free(t0);
@@ -10437,21 +10408,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI);
return;
}
- op_ld_lw(t1, t0, ctx);
+ tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- op_ld_lw(t1, t0, ctx);
+ tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd+1);
opn = "lwp";
break;
case SWP:
gen_load_gpr(t1, rd);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd+1);
- op_st_sw(t1, t0, ctx);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
opn = "swp";
break;
#ifdef TARGET_MIPS64
@@ -10460,21 +10431,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI);
return;
}
- op_ld_ld(t1, t0, ctx);
+ tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- op_ld_ld(t1, t0, ctx);
+ tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd+1);
opn = "ldp";
break;
case SDP:
gen_load_gpr(t1, rd);
- op_st_sd(t1, t0, ctx);
+ tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd+1);
- op_st_sd(t1, t0, ctx);
+ tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
opn = "sdp";
break;
#endif
--
1.7.10.4
next prev parent reply other threads:[~2012-10-30 0:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-30 0:11 [Qemu-devel] [PATCH v2 00/19] target-mips: misc fixes and optimizations Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 01/19] target-mips: correctly restore btarget upon exception Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 02/19] target-mips: do not save CPU state when using retranslation Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 03/19] softfloat: implement fused multiply-add NaN propagation for MIPS Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 04/19] target-mips: use the softfloat floatXX_muladd functions Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 05/19] target-mips: keep softfloat exception set to 0 between instructions Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 06/19] target-mips: fix FPU exceptions Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 07/19] target-mips: cleanup float to int conversion helpers Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 08/19] target-mips: use softfloat constants when possible Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 09/19] target-mips: restore CPU state after an FPU exception Aurelien Jarno
2012-10-30 0:12 ` Aurelien Jarno [this message]
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 12/19] target-mips: simplify load/store microMIPS helpers Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 13/19] target-mips: implement unaligned loads using TCG Aurelien Jarno
2012-10-30 18:59 ` Blue Swirl
2012-10-30 20:00 ` Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 14/19] target-mips: don't use local temps for store conditional Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 15/19] target-mips: implement movn/movz using movcond Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 16/19] target-mips: optimize ddiv/ddivu/div/divu with movcond Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 17/19] target-mips: use deposit instead of hardcoded version Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 18/19] target-mips: fix TLBR wrt SEGMask Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 19/19] target-mips: don't flush extra TLB on permissions upgrade Aurelien Jarno
2012-10-31 6:37 ` [Qemu-devel] [PATCH v2 00/19] target-mips: misc fixes and optimizations Richard Henderson
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