From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRO-00079N-2u for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSzRM-0005BI-1S for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:21 -0400 Received: from hall.aurel32.net ([88.191.126.93]:39634) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRL-0005AP-Rs for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:19 -0400 From: Aurelien Jarno Date: Tue, 30 Oct 2012 01:12:04 +0100 Message-Id: <1351555932-19695-12-git-send-email-aurelien@aurel32.net> In-Reply-To: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> References: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno Only allocate t1 when needed. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 4485a81..c46129d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1136,7 +1136,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } t0 = tcg_temp_new(); - t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, base, offset); switch (opc) { @@ -1159,29 +1158,35 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LDL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldl"; break; case OPC_LDR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldr"; break; case OPC_LDPC: - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "ldpc"; break; #endif case OPC_LWPC: - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lwpc"; @@ -1213,16 +1218,20 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LWL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwl"; break; case OPC_LWR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwr"; break; case OPC_LL: @@ -1235,7 +1244,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); - tcg_temp_free(t1); } /* Store */ -- 1.7.10.4