From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRM-00078Q-JK for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSzRL-0005A2-7K for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:20 -0400 Received: from hall.aurel32.net ([88.191.126.93]:39627) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRL-00059W-0h for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:19 -0400 From: Aurelien Jarno Date: Tue, 30 Oct 2012 01:11:54 +0100 Message-Id: <1351555932-19695-2-git-send-email-aurelien@aurel32.net> In-Reply-To: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> References: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v2 01/19] target-mips: correctly restore btarget upon exception List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno When the CPU state is restored through retranslation after an exception, btarget should also be restored. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index ed55e26..3cf4ca1 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -578,6 +578,7 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; +static target_ulong gen_opc_btarget[OPC_BUF_SIZE]; #include "gen-icount.h" @@ -12859,6 +12860,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, } gen_opc_pc[lj] = ctx.pc; gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; + gen_opc_btarget[lj] = ctx.btarget; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -13274,4 +13276,13 @@ void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) env->active_tc.PC = gen_opc_pc[pc_pos]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= gen_opc_hflags[pc_pos]; + switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + env->btarget = gen_opc_btarget[pc_pos]; + break; + } } -- 1.7.10.4