From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 07/19] target-mips: cleanup float to int conversion helpers
Date: Tue, 30 Oct 2012 01:12:00 +0100 [thread overview]
Message-ID: <1351555932-19695-8-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1351555932-19695-1-git-send-email-aurelien@aurel32.net>
Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/op_helper.c | 118 +++++++++++++++++++++++++++++++----------------
1 file changed, 79 insertions(+), 39 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7981ea2..d3a317b 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2509,9 +2509,11 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
uint64_t dt2;
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2520,9 +2522,11 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
uint64_t dt2;
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2613,8 +2617,10 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
return wt2;
}
@@ -2623,9 +2629,11 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
uint32_t wt2;
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2636,9 +2644,11 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2649,9 +2659,11 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2662,9 +2674,11 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2675,9 +2689,11 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2686,9 +2702,11 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
uint64_t dt2;
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2697,9 +2715,11 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
uint64_t dt2;
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2708,9 +2728,11 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
uint32_t wt2;
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2719,9 +2741,11 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
uint32_t wt2;
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2732,9 +2756,11 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2745,9 +2771,11 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2758,9 +2786,11 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2771,9 +2801,11 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2784,9 +2816,11 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2797,9 +2831,11 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
dt2 = FLOAT_SNAN64;
+ }
+ update_fcr31(env);
return dt2;
}
@@ -2810,9 +2846,11 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
@@ -2823,9 +2861,11 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
RESTORE_ROUNDING_MODE;
- update_fcr31(env);
- if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
+ if (get_float_exception_flags(&env->active_fpu.fp_status)
+ & (float_flag_invalid | float_flag_overflow)) {
wt2 = FLOAT_SNAN32;
+ }
+ update_fcr31(env);
return wt2;
}
--
1.7.10.4
next prev parent reply other threads:[~2012-10-30 0:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-30 0:11 [Qemu-devel] [PATCH v2 00/19] target-mips: misc fixes and optimizations Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 01/19] target-mips: correctly restore btarget upon exception Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 02/19] target-mips: do not save CPU state when using retranslation Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 03/19] softfloat: implement fused multiply-add NaN propagation for MIPS Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 04/19] target-mips: use the softfloat floatXX_muladd functions Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 05/19] target-mips: keep softfloat exception set to 0 between instructions Aurelien Jarno
2012-10-30 0:11 ` [Qemu-devel] [PATCH v2 06/19] target-mips: fix FPU exceptions Aurelien Jarno
2012-10-30 0:12 ` Aurelien Jarno [this message]
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 08/19] target-mips: use softfloat constants when possible Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 09/19] target-mips: restore CPU state after an FPU exception Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 10/19] target-mips: cleanup load/store operations Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 12/19] target-mips: simplify load/store microMIPS helpers Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 13/19] target-mips: implement unaligned loads using TCG Aurelien Jarno
2012-10-30 18:59 ` Blue Swirl
2012-10-30 20:00 ` Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 14/19] target-mips: don't use local temps for store conditional Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 15/19] target-mips: implement movn/movz using movcond Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 16/19] target-mips: optimize ddiv/ddivu/div/divu with movcond Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 17/19] target-mips: use deposit instead of hardcoded version Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 18/19] target-mips: fix TLBR wrt SEGMask Aurelien Jarno
2012-10-30 0:12 ` [Qemu-devel] [PATCH v2 19/19] target-mips: don't flush extra TLB on permissions upgrade Aurelien Jarno
2012-10-31 6:37 ` [Qemu-devel] [PATCH v2 00/19] target-mips: misc fixes and optimizations Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1351555932-19695-8-git-send-email-aurelien@aurel32.net \
--to=aurelien@aurel32.net \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).