From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzX8-00030e-Up for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:18:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSzX7-0006bk-Md for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:18:18 -0400 Received: from hall.aurel32.net ([88.191.126.93]:39668) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzX7-0006be-GC for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:18:17 -0400 From: y@ohm.aurel32.net Date: Tue, 30 Oct 2012 01:18:10 +0100 Message-Id: <1351556293-20322-1-git-send-email-y> Subject: [Qemu-devel] [PATCH v2 0/3] tcg/arm: misc fixes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno From: Aurelien Jarno This patch series fixes the TCG arm backend for the MIPS target, as well as for big endian targets when not using the ARMv6+ instructions set. The corresponding patches are candidate for a stable release. -- Changes v1 -> v2: - patch 1: - added an assert to make sure the TLB offset fits within 24 bits - added an assert to make sure both registers are different in ldr_wb - patches 4 and 5 (optimizations) have been dropped and will be resubmitted again (when I can find some time to work on them). Aurelien Jarno (3): tcg/arm: fix TLB access in qemu-ld/st ops tcg/arm: fix cross-endian qemu_st16 target-openrisc: remove conflicting definitions from cpu.h target-openrisc/cpu.h | 18 --------- tcg/arm/tcg-target.c | 97 ++++++++++++++++++++++++++++++------------------- 2 files changed, 59 insertions(+), 56 deletions(-) -- 1.7.10.4