qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Andreas Färber" <afaerber@suse.de>, anthony@codemonkey.ws
Subject: [Qemu-devel] [PATCH 18/35] ppc: Pass PowerPCCPU to {ppc6xx, ppc970, power7, ppc40x, ppce500}_set_irq()
Date: Wed, 31 Oct 2012 01:59:49 +0100	[thread overview]
Message-ID: <1351645206-3041-19-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1351645206-3041-1-git-send-email-afaerber@suse.de>

Needed for changing qemu_cpu_kick() argument type to CPUState and
for moving halted field into CPUState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 hw/ppc.c |   55 +++++++++++++++++++++++++++++++++++--------------------
 1 Datei geändert, 35 Zeilen hinzugefügt(+), 20 Zeilen entfernt(-)

diff --git a/hw/ppc.c b/hw/ppc.c
index 98546de..ada100b 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -75,9 +75,10 @@ void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
 }
 
 /* PowerPC 6xx / 7xx internal IRQ controller */
-static void ppc6xx_set_irq (void *opaque, int pin, int level)
+static void ppc6xx_set_irq(void *opaque, int pin, int level)
 {
-    CPUPPCState *env = opaque;
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
     int cur_level;
 
     LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -151,17 +152,20 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
     }
 }
 
-void ppc6xx_irq_init (CPUPPCState *env)
+void ppc6xx_irq_init(CPUPPCState *env)
 {
-    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
                                                   PPC6xx_INPUT_NB);
 }
 
 #if defined(TARGET_PPC64)
 /* PowerPC 970 internal IRQ controller */
-static void ppc970_set_irq (void *opaque, int pin, int level)
+static void ppc970_set_irq(void *opaque, int pin, int level)
 {
-    CPUPPCState *env = opaque;
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
     int cur_level;
 
     LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -233,16 +237,19 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
     }
 }
 
-void ppc970_irq_init (CPUPPCState *env)
+void ppc970_irq_init(CPUPPCState *env)
 {
-    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
                                                   PPC970_INPUT_NB);
 }
 
 /* POWER7 internal IRQ controller */
-static void power7_set_irq (void *opaque, int pin, int level)
+static void power7_set_irq(void *opaque, int pin, int level)
 {
-    CPUPPCState *env = opaque;
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
 
     LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
                 env, pin, level);
@@ -266,17 +273,20 @@ static void power7_set_irq (void *opaque, int pin, int level)
     }
 }
 
-void ppcPOWER7_irq_init (CPUPPCState *env)
+void ppcPOWER7_irq_init(CPUPPCState *env)
 {
-    env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+    env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
                                                   POWER7_INPUT_NB);
 }
 #endif /* defined(TARGET_PPC64) */
 
 /* PowerPC 40x internal IRQ controller */
-static void ppc40x_set_irq (void *opaque, int pin, int level)
+static void ppc40x_set_irq(void *opaque, int pin, int level)
 {
-    CPUPPCState *env = opaque;
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
     int cur_level;
 
     LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -346,16 +356,19 @@ static void ppc40x_set_irq (void *opaque, int pin, int level)
     }
 }
 
-void ppc40x_irq_init (CPUPPCState *env)
+void ppc40x_irq_init(CPUPPCState *env)
 {
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
     env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
-                                                  env, PPC40x_INPUT_NB);
+                                                  cpu, PPC40x_INPUT_NB);
 }
 
 /* PowerPC E500 internal IRQ controller */
-static void ppce500_set_irq (void *opaque, int pin, int level)
+static void ppce500_set_irq(void *opaque, int pin, int level)
 {
-    CPUPPCState *env = opaque;
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
     int cur_level;
 
     LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -407,10 +420,12 @@ static void ppce500_set_irq (void *opaque, int pin, int level)
     }
 }
 
-void ppce500_irq_init (CPUPPCState *env)
+void ppce500_irq_init(CPUPPCState *env)
 {
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
     env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
-                                        env, PPCE500_INPUT_NB);
+                                                  cpu, PPCE500_INPUT_NB);
 }
 /*****************************************************************************/
 /* PowerPC time base and decrementer emulation */
-- 
1.7.10.4

  parent reply	other threads:[~2012-10-31  1:00 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-31  0:59 [Qemu-devel] [PULL] QOM CPUState patch queue 2012-10-31 Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 01/35] target-i386: cpu_x86_register(): report error from property setter Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 02/35] target-i386: If x86_cpu_realize() failed, report error and do cleanup Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 03/35] target-i386: Initialize APIC at CPU level Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 04/35] target-i386: Inline APIC cpu_env property setting Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 05/35] apic: Store X86CPU in APICCommonState Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 06/35] target-i386: Pass X86CPU to cpu_x86_load_seg_cache_sipi() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 07/35] cpus: Pass CPUState to qemu_cpu_is_self() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 08/35] cpus: Pass CPUState to qemu_cpu_kick_thread() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 09/35] cpu: Move created field to CPUState Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 10/35] cpu: Move stop " Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 11/35] ppce500_spin: Store PowerPCCPU in SpinKick Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 12/35] cpu: Move stopped field to CPUState Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 13/35] cpus: Pass CPUState to cpu_is_stopped() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 14/35] cpus: Pass CPUState to cpu_can_run() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 15/35] cpu: Move halt_cond to CPUState Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 16/35] cpus: Pass CPUState to qemu_tcg_cpu_thread_fn Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 17/35] cpus: Pass CPUState to qemu_tcg_init_vcpu() Andreas Färber
2012-10-31  0:59 ` Andreas Färber [this message]
2012-10-31  0:59 ` [Qemu-devel] [PATCH 19/35] target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 20/35] cpus: Pass CPUState to qemu_cpu_kick() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 21/35] cpu: Move queued_work_{first, last} to CPUState Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 22/35] cpus: Pass CPUState to flush_queued_work() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 23/35] cpus: Pass CPUState to qemu_wait_io_event_common() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 24/35] xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 25/35] target-ppc: Pass PowerPCCPU to powerpc_excp() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 26/35] target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 27/35] spapr: Pass PowerPCCPU to spapr_hypercall() Andreas Färber
2012-10-31  0:59 ` [Qemu-devel] [PATCH 28/35] spapr: Pass PowerPCCPU to hypercalls Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 29/35] cpus: Pass CPUState to [qemu_]cpu_has_work() Andreas Färber
2012-10-31  1:29   ` Richard Henderson
2012-10-31 21:05   ` Aurelien Jarno
2012-10-31 21:37     ` Andreas Färber
2012-10-31 21:47       ` Aurelien Jarno
2012-10-31  1:00 ` [Qemu-devel] [PATCH 30/35] target-i386: Pass X86CPU to kvm_mce_inject() Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 31/35] target-i386: Pass X86CPU to cpu_x86_inject_mce() Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 32/35] cpus: Pass CPUState to run_on_cpu() Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 33/35] cpu: Move thread_id to CPUState Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 34/35] target-i386: Pass X86CPU to kvm_get_mp_state() Andreas Färber
2012-10-31  1:00 ` [Qemu-devel] [PATCH 35/35] target-i386: Pass X86CPU to kvm_handle_halt() Andreas Färber
2012-10-31  3:15 ` [Qemu-devel] [PULL] QOM CPUState patch queue 2012-10-31 Andreas Färber
2012-11-01 19:32 ` Anthony Liguori

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1351645206-3041-19-git-send-email-afaerber@suse.de \
    --to=afaerber@suse.de \
    --cc=anthony@codemonkey.ws \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).