From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTMfk-00082v-DX for qemu-devel@nongnu.org; Tue, 30 Oct 2012 21:00:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TTMfa-0005I3-71 for qemu-devel@nongnu.org; Tue, 30 Oct 2012 21:00:43 -0400 Received: from cantor2.suse.de ([195.135.220.15]:52366 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTMfZ-0005Gy-Pu for qemu-devel@nongnu.org; Tue, 30 Oct 2012 21:00:34 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 31 Oct 2012 01:59:36 +0100 Message-Id: <1351645206-3041-6-git-send-email-afaerber@suse.de> In-Reply-To: <1351645206-3041-1-git-send-email-afaerber@suse.de> References: <1351645206-3041-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 05/35] apic: Store X86CPU in APICCommonState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , anthony@codemonkey.ws Prepares for using a link<> property to connect APIC with CPU and for changing the CPU APIs to CPUState. Resolve Coding Style warnings by moving the closing parenthesis of foreach_apic() macro to next line. Signed-off-by: Andreas F=C3=A4rber Reviewed-by: Igor Mammedov --- hw/apic.c | 38 +++++++++++++++++++++----------------- hw/apic_common.c | 4 ++-- hw/apic_internal.h | 3 ++- hw/kvm/apic.c | 8 ++++---- target-i386/cpu.c | 2 +- 5 Dateien ge=C3=A4ndert, 30 Zeilen hinzugef=C3=BCgt(+), 25 Zeilen entfer= nt(-) diff --git a/hw/apic.c b/hw/apic.c index 49f0015..99e84f9 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -107,7 +107,7 @@ static void apic_sync_vapic(APICCommonState *s, int s= ync_type) length =3D offsetof(VAPICState, enabled) - offsetof(VAPICState, = isr); =20 if (sync_type & SYNC_TO_VAPIC) { - assert(qemu_cpu_is_self(s->cpu_env)); + assert(qemu_cpu_is_self(&s->cpu->env)); =20 vapic_state.tpr =3D s->tpr; vapic_state.enabled =3D 1; @@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, = int vector) =20 switch ((lvt >> 8) & 7) { case APIC_DM_SMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI); break; =20 case APIC_DM_NMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI); break; =20 case APIC_DM_EXTINT: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; =20 case APIC_DM_FIXED: @@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) reset_bit(s->irr, lvt & 0xff); /* fall through */ case APIC_DM_EXTINT: - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; } } @@ -248,18 +248,22 @@ static void apic_bus_deliver(const uint32_t *delive= r_bitmask, =20 case APIC_DM_SMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI) + ); return; =20 case APIC_DM_NMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI) + ); return; =20 case APIC_DM_INIT: /* normal INIT IPI sent to processors */ foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT= _INIT) ); + cpu_interrupt(&apic_iter->cpu->env, + CPU_INTERRUPT_INIT) + ); return; =20 case APIC_DM_EXTINT: @@ -293,7 +297,7 @@ static void apic_set_base(APICCommonState *s, uint64_= t val) /* if disabled, cannot be enabled again */ if (!(val & MSR_IA32_APICBASE_ENABLE)) { s->apicbase &=3D ~MSR_IA32_APICBASE_ENABLE; - cpu_clear_apic_feature(s->cpu_env); + cpu_clear_apic_feature(&s->cpu->env); s->spurious_vec &=3D ~APIC_SV_ENABLE; } } @@ -362,10 +366,10 @@ static void apic_update_irq(APICCommonState *s) if (!(s->spurious_vec & APIC_SV_ENABLE)) { return; } - if (!qemu_cpu_is_self(s->cpu_env)) { - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL); + if (!qemu_cpu_is_self(&s->cpu->env)) { + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL); } else if (apic_irq_pending(s) > 0) { - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); } } =20 @@ -472,18 +476,18 @@ static void apic_get_delivery_bitmask(uint32_t *del= iver_bitmask, static void apic_startup(APICCommonState *s, int vector_num) { s->sipi_vector =3D vector_num; - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); } =20 void apic_sipi(DeviceState *d) { APICCommonState *s =3D DO_UPCAST(APICCommonState, busdev.qdev, d); =20 - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); =20 if (!s->wait_for_sipi) return; - cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); + cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector); s->wait_for_sipi =3D 0; } =20 @@ -672,7 +676,7 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr a= ddr) case 0x08: apic_sync_vapic(s, SYNC_FROM_VAPIC); if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); } val =3D s->tpr; break; @@ -774,7 +778,7 @@ static void apic_mem_writel(void *opaque, hwaddr addr= , uint32_t val) break; case 0x08: if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); } s->tpr =3D val; apic_sync_vapic(s, SYNC_TO_VAPIC); diff --git a/hw/apic_common.c b/hw/apic_common.c index b13f23c..5f54276 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -103,7 +103,7 @@ void apic_handle_tpr_access_report(DeviceState *d, ta= rget_ulong ip, { APICCommonState *s =3D DO_UPCAST(APICCommonState, busdev.qdev, d); =20 - vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access); + vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access); } =20 void apic_report_irq_delivered(int delivered) @@ -217,7 +217,7 @@ static void apic_reset_common(DeviceState *d) APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); bool bsp; =20 - bsp =3D cpu_is_bsp(x86_env_get_cpu(s->cpu_env)); + bsp =3D cpu_is_bsp(s->cpu); s->apicbase =3D 0xfee00000 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; =20 diff --git a/hw/apic_internal.h b/hw/apic_internal.h index 30932a3..79e2de2 100644 --- a/hw/apic_internal.h +++ b/hw/apic_internal.h @@ -95,8 +95,9 @@ typedef struct APICCommonClass =20 struct APICCommonState { SysBusDevice busdev; + MemoryRegion io_memory; - void *cpu_env; + X86CPU *cpu; uint32_t apicbase; uint8_t id; uint8_t arb_id; diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index dbac7ff..e4a7307 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -104,7 +104,7 @@ static void kvm_apic_enable_tpr_reporting(APICCommonS= tate *s, bool enable) .enabled =3D enable }; =20 - kvm_vcpu_ioctl(s->cpu_env, KVM_TPR_ACCESS_REPORTING, &ctl); + kvm_vcpu_ioctl(&s->cpu->env, KVM_TPR_ACCESS_REPORTING, &ctl); } =20 static void kvm_apic_vapic_base_update(APICCommonState *s) @@ -114,7 +114,7 @@ static void kvm_apic_vapic_base_update(APICCommonStat= e *s) }; int ret; =20 - ret =3D kvm_vcpu_ioctl(s->cpu_env, KVM_SET_VAPIC_ADDR, &vapid_addr); + ret =3D kvm_vcpu_ioctl(&s->cpu->env, KVM_SET_VAPIC_ADDR, &vapid_addr= ); if (ret < 0) { fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", strerror(-ret)); @@ -125,7 +125,7 @@ static void kvm_apic_vapic_base_update(APICCommonStat= e *s) static void do_inject_external_nmi(void *data) { APICCommonState *s =3D data; - CPUX86State *env =3D s->cpu_env; + CPUX86State *env =3D &s->cpu->env; uint32_t lvt; int ret; =20 @@ -143,7 +143,7 @@ static void do_inject_external_nmi(void *data) =20 static void kvm_apic_external_nmi(APICCommonState *s) { - run_on_cpu(s->cpu_env, do_inject_external_nmi, s); + run_on_cpu(&s->cpu->env, do_inject_external_nmi, s); } =20 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, diff --git a/target-i386/cpu.c b/target-i386/cpu.c index c30cc79..156e919 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1913,7 +1913,7 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **= errp) qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); /* TODO: convert to link<> */ apic =3D APIC_COMMON(env->apic_state); - apic->cpu_env =3D env; + apic->cpu =3D cpu; =20 if (qdev_init(env->apic_state)) { error_setg(errp, "APIC device '%s' could not be initialized", --=20 1.7.10.4