[Qemu-devel] [PATCH 22/29] pci_bridge_dev: add qom property for pci-bridge state

[Michael Roth <mdroth@linux.vnet.ibm.com>]

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
 hw/pci.c            |    1 +
 hw/pci.h            |    3 ++-
 hw/pci_bridge_dev.c |   29 +++++++++++++++++++++++++++++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/hw/pci.c b/hw/pci.c
index e0b3f4f..d27659c 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -35,6 +35,7 @@
 #include "msix.h"
 #include "exec-memory.h"
 #include "qidl.h"
+#include "shpc.h"
 
 QIDL_ENABLE()
 
diff --git a/hw/pci.h b/hw/pci.h
index e356fbd..9a08ebc 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -263,7 +263,8 @@ QIDL_DECLARE_PUBLIC(PCIDevice) {
     PCIExpressDevice q_broken exp; /* TODO: qidl, is PCIEAERLog guest-visible? */
 
     /* SHPC */
-    SHPCDevice q_broken *shpc; /* TODO: qidl, needed for pci-bridge support */
+    bool has_shpc;
+    SHPCDevice *shpc q_optional;
 
     /* Location of option rom */
     char q_property("romfile") *romfile;
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
index d793857..c89b04f 100644
--- a/hw/pci_bridge_dev.c
+++ b/hw/pci_bridge_dev.c
@@ -28,6 +28,8 @@
 #include "pci_internals.h"
 #include "qidl.h"
 
+QIDL_ENABLE()
+
 #define REDHAT_PCI_VENDOR_ID 0x1b36
 #define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
 #define PCI_BRIDGE_DEV_DEVICE_ID 0x1
@@ -50,6 +52,28 @@ static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
     return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
 }
 
+static void pci_bridge_dev_get_state(Object *obj, Visitor *v, void *opaque,
+                                     const char *name, Error **errp)
+{
+    PCIDevice *pci = PCI_DEVICE(obj);
+    PCIBridge *br = DO_UPCAST(PCIBridge, dev, pci);
+    PCIBridgeDev *d = DO_UPCAST(PCIBridgeDev, bridge, br);
+
+    QIDL_VISIT_TYPE(PCIBridgeDev, v, &d, name, errp);
+}
+
+static void pci_bridge_dev_set_state(Object *obj, Visitor *v, void *opaque,
+                                     const char *name, Error **errp)
+{
+    PCIDevice *pci = PCI_DEVICE(obj);
+    PCIBridge *br = DO_UPCAST(PCIBridge, dev, pci);
+    PCIBridgeDev *d = DO_UPCAST(PCIBridgeDev, bridge, br);
+
+    QIDL_VISIT_TYPE(PCIBridgeDev, v, &d, name, errp);
+    shpc_post_load(pci);
+}
+
+
 static int pci_bridge_dev_initfn(PCIDevice *dev)
 {
     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
@@ -66,6 +90,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
     if (err) {
         goto shpc_error;
     }
+    dev->has_shpc = true;
     err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
     if (err) {
         goto slotid_error;
@@ -82,6 +107,10 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
 		     PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
     dev->config[PCI_INTERRUPT_PIN] = 0x1;
+    object_property_add(OBJECT(dev), "state", "PCIBridgeDev",
+                        pci_bridge_dev_get_state, pci_bridge_dev_set_state,
+                        NULL, NULL, NULL);
+    QIDL_SCHEMA_ADD_LINK(PCIBridgeDev, OBJECT(dev), "state_schema", NULL);
     return 0;
 msi_error:
     slotid_cap_cleanup(dev);
-- 
1.7.9.5