From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTuSh-0005GV-01 for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TTuSY-0006Y5-2Z for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:30 -0400 Received: from mail-ie0-f173.google.com ([209.85.223.173]:62691) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTuSX-00064D-RL for qemu-devel@nongnu.org; Thu, 01 Nov 2012 09:05:22 -0400 Received: by mail-ie0-f173.google.com with SMTP id 17so3616429iea.4 for ; Thu, 01 Nov 2012 06:05:21 -0700 (PDT) Sender: fluxion From: Michael Roth Date: Thu, 1 Nov 2012 08:04:24 -0500 Message-Id: <1351775071-7644-23-git-send-email-mdroth@linux.vnet.ibm.com> In-Reply-To: <1351775071-7644-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1351775071-7644-1-git-send-email-mdroth@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 22/29] pci_bridge_dev: add qom property for pci-bridge state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kwolf@redhat.com, peter.maydell@linaro.org, aliguori@us.ibm.com, quintela@redhat.com, blauwirbel@gmail.com, pbonzini@redhat.com Signed-off-by: Michael Roth --- hw/pci.c | 1 + hw/pci.h | 3 ++- hw/pci_bridge_dev.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/pci.c b/hw/pci.c index e0b3f4f..d27659c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -35,6 +35,7 @@ #include "msix.h" #include "exec-memory.h" #include "qidl.h" +#include "shpc.h" QIDL_ENABLE() diff --git a/hw/pci.h b/hw/pci.h index e356fbd..9a08ebc 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -263,7 +263,8 @@ QIDL_DECLARE_PUBLIC(PCIDevice) { PCIExpressDevice q_broken exp; /* TODO: qidl, is PCIEAERLog guest-visible? */ /* SHPC */ - SHPCDevice q_broken *shpc; /* TODO: qidl, needed for pci-bridge support */ + bool has_shpc; + SHPCDevice *shpc q_optional; /* Location of option rom */ char q_property("romfile") *romfile; diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c index d793857..c89b04f 100644 --- a/hw/pci_bridge_dev.c +++ b/hw/pci_bridge_dev.c @@ -28,6 +28,8 @@ #include "pci_internals.h" #include "qidl.h" +QIDL_ENABLE() + #define REDHAT_PCI_VENDOR_ID 0x1b36 #define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID #define PCI_BRIDGE_DEV_DEVICE_ID 0x1 @@ -50,6 +52,28 @@ static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num) return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS; } +static void pci_bridge_dev_get_state(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + PCIDevice *pci = PCI_DEVICE(obj); + PCIBridge *br = DO_UPCAST(PCIBridge, dev, pci); + PCIBridgeDev *d = DO_UPCAST(PCIBridgeDev, bridge, br); + + QIDL_VISIT_TYPE(PCIBridgeDev, v, &d, name, errp); +} + +static void pci_bridge_dev_set_state(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + PCIDevice *pci = PCI_DEVICE(obj); + PCIBridge *br = DO_UPCAST(PCIBridge, dev, pci); + PCIBridgeDev *d = DO_UPCAST(PCIBridgeDev, bridge, br); + + QIDL_VISIT_TYPE(PCIBridgeDev, v, &d, name, errp); + shpc_post_load(pci); +} + + static int pci_bridge_dev_initfn(PCIDevice *dev) { PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); @@ -66,6 +90,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) if (err) { goto shpc_error; } + dev->has_shpc = true; err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0); if (err) { goto slotid_error; @@ -82,6 +107,10 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); dev->config[PCI_INTERRUPT_PIN] = 0x1; + object_property_add(OBJECT(dev), "state", "PCIBridgeDev", + pci_bridge_dev_get_state, pci_bridge_dev_set_state, + NULL, NULL, NULL); + QIDL_SCHEMA_ADD_LINK(PCIBridgeDev, OBJECT(dev), "state_schema", NULL); return 0; msi_error: slotid_cap_cleanup(dev); -- 1.7.9.5