* [Qemu-devel] [PATCH 1/2] x86/cpu: name new CPUID bits
@ 2012-11-02 13:21 Boris Ostrovsky
2012-11-14 17:57 ` Eduardo Habkost
0 siblings, 1 reply; 2+ messages in thread
From: Boris Ostrovsky @ 2012-11-02 13:21 UTC (permalink / raw)
To: qemu-devel; +Cc: boris.ostrovsky, osp, ehabkost
From: Andre Przywara <osp@andrep.de>
Update QEMU's knowledge of CPUID bit names. This allows to
enable/disable those new features on QEMU's command line when
using KVM and prepares future feature enablement in QEMU.
This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
FSGSBASE, BMI1, AVX2, BMI2, ERMS, InvPCID, RTM, RDSeed and ADX.
Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel
for the leaf 7 bits.
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
---
target-i386/cpu.c | 16 ++++++++--------
target-i386/cpu.h | 21 +++++++++++++++++++++
2 files changed, 29 insertions(+), 8 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index d4f2e65..ec9b71f 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -59,7 +59,7 @@ static const char *ext_feature_name[] = {
NULL, "pcid", "dca", "sse4.1|sse4_1",
"sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
"tsc-deadline", "aes", "xsave", "osxsave",
- "avx", NULL, NULL, "hypervisor",
+ "avx", "f16c", "rdrand", "hypervisor",
};
/* Feature names that are already defined on feature_name[] but are set on
* CPUID[8000_0001].EDX on AMD CPUs don't have their names on
@@ -80,10 +80,10 @@ static const char *ext3_feature_name[] = {
"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
"cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
"3dnowprefetch", "osvw", "ibs", "xop",
- "skinit", "wdt", NULL, NULL,
- "fma4", NULL, "cvt16", "nodeid_msr",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
+ "skinit", "wdt", NULL, "lwp",
+ "fma4", "tce", NULL, "nodeid_msr",
+ NULL, "tbm", "topoext", "perfctr_core",
+ "perfctr_nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
};
@@ -106,9 +106,9 @@ static const char *svm_feature_name[] = {
};
static const char *cpuid_7_0_ebx_feature_name[] = {
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep",
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
+ "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
+ "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
+ NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index de33303..a597e03 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -403,6 +403,7 @@
#define CPUID_EXT_TM2 (1 << 8)
#define CPUID_EXT_SSSE3 (1 << 9)
#define CPUID_EXT_CID (1 << 10)
+#define CPUID_EXT_FMA (1 << 12)
#define CPUID_EXT_CX16 (1 << 13)
#define CPUID_EXT_XTPR (1 << 14)
#define CPUID_EXT_PDCM (1 << 15)
@@ -417,6 +418,8 @@
#define CPUID_EXT_XSAVE (1 << 26)
#define CPUID_EXT_OSXSAVE (1 << 27)
#define CPUID_EXT_AVX (1 << 28)
+#define CPUID_EXT_F16C (1 << 29)
+#define CPUID_EXT_RDRAND (1 << 30)
#define CPUID_EXT_HYPERVISOR (1 << 31)
#define CPUID_EXT2_FPU (1 << 0)
@@ -472,7 +475,15 @@
#define CPUID_EXT3_IBS (1 << 10)
#define CPUID_EXT3_XOP (1 << 11)
#define CPUID_EXT3_SKINIT (1 << 12)
+#define CPUID_EXT3_WDT (1 << 13)
+#define CPUID_EXT3_LWP (1 << 15)
#define CPUID_EXT3_FMA4 (1 << 16)
+#define CPUID_EXT3_TCE (1 << 17)
+#define CPUID_EXT3_NODEID (1 << 19)
+#define CPUID_EXT3_TBM (1 << 21)
+#define CPUID_EXT3_TOPOEXT (1 << 22)
+#define CPUID_EXT3_PERFCORE (1 << 23)
+#define CPUID_EXT3_PERFNB (1 << 24)
#define CPUID_SVM_NPT (1 << 0)
#define CPUID_SVM_LBRV (1 << 1)
@@ -485,7 +496,17 @@
#define CPUID_SVM_PAUSEFILTER (1 << 10)
#define CPUID_SVM_PFTHRESHOLD (1 << 12)
+#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
+#define CPUID_7_0_EBX_BMI1 (1 << 3)
+#define CPUID_7_0_EBX_HLE (1 << 4)
+#define CPUID_7_0_EBX_AVX2 (1 << 5)
#define CPUID_7_0_EBX_SMEP (1 << 7)
+#define CPUID_7_0_EBX_BMI2 (1 << 8)
+#define CPUID_7_0_EBX_ERMS (1 << 9)
+#define CPUID_7_0_EBX_INVPCID (1 << 10)
+#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_RDSEED (1 << 18)
+#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] x86/cpu: name new CPUID bits
2012-11-02 13:21 [Qemu-devel] [PATCH 1/2] x86/cpu: name new CPUID bits Boris Ostrovsky
@ 2012-11-14 17:57 ` Eduardo Habkost
0 siblings, 0 replies; 2+ messages in thread
From: Eduardo Habkost @ 2012-11-14 17:57 UTC (permalink / raw)
To: Boris Ostrovsky; +Cc: boris.ostrovsky, osp, qemu-devel
On Fri, Nov 02, 2012 at 09:21:26AM -0400, Boris Ostrovsky wrote:
> From: Andre Przywara <osp@andrep.de>
>
> Update QEMU's knowledge of CPUID bit names. This allows to
> enable/disable those new features on QEMU's command line when
> using KVM and prepares future feature enablement in QEMU.
>
> This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
> FSGSBASE, BMI1, AVX2, BMI2, ERMS, InvPCID, RTM, RDSeed and ADX.
>
> Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel
> for the leaf 7 bits.
>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/cpu.c | 16 ++++++++--------
> target-i386/cpu.h | 21 +++++++++++++++++++++
> 2 files changed, 29 insertions(+), 8 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index d4f2e65..ec9b71f 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -59,7 +59,7 @@ static const char *ext_feature_name[] = {
> NULL, "pcid", "dca", "sse4.1|sse4_1",
> "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
> "tsc-deadline", "aes", "xsave", "osxsave",
> - "avx", NULL, NULL, "hypervisor",
> + "avx", "f16c", "rdrand", "hypervisor",
> };
> /* Feature names that are already defined on feature_name[] but are set on
> * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
> @@ -80,10 +80,10 @@ static const char *ext3_feature_name[] = {
> "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
> "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
> "3dnowprefetch", "osvw", "ibs", "xop",
> - "skinit", "wdt", NULL, NULL,
> - "fma4", NULL, "cvt16", "nodeid_msr",
> - NULL, NULL, NULL, NULL,
> - NULL, NULL, NULL, NULL,
> + "skinit", "wdt", NULL, "lwp",
> + "fma4", "tce", NULL, "nodeid_msr",
> + NULL, "tbm", "topoext", "perfctr_core",
> + "perfctr_nb", NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> };
>
> @@ -106,9 +106,9 @@ static const char *svm_feature_name[] = {
> };
>
> static const char *cpuid_7_0_ebx_feature_name[] = {
> - NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep",
> - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
> - NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
> + "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
> + "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
> + NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
> NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
> };
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index de33303..a597e03 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -403,6 +403,7 @@
> #define CPUID_EXT_TM2 (1 << 8)
> #define CPUID_EXT_SSSE3 (1 << 9)
> #define CPUID_EXT_CID (1 << 10)
> +#define CPUID_EXT_FMA (1 << 12)
> #define CPUID_EXT_CX16 (1 << 13)
> #define CPUID_EXT_XTPR (1 << 14)
> #define CPUID_EXT_PDCM (1 << 15)
> @@ -417,6 +418,8 @@
> #define CPUID_EXT_XSAVE (1 << 26)
> #define CPUID_EXT_OSXSAVE (1 << 27)
> #define CPUID_EXT_AVX (1 << 28)
> +#define CPUID_EXT_F16C (1 << 29)
> +#define CPUID_EXT_RDRAND (1 << 30)
> #define CPUID_EXT_HYPERVISOR (1 << 31)
>
> #define CPUID_EXT2_FPU (1 << 0)
> @@ -472,7 +475,15 @@
> #define CPUID_EXT3_IBS (1 << 10)
> #define CPUID_EXT3_XOP (1 << 11)
> #define CPUID_EXT3_SKINIT (1 << 12)
> +#define CPUID_EXT3_WDT (1 << 13)
> +#define CPUID_EXT3_LWP (1 << 15)
> #define CPUID_EXT3_FMA4 (1 << 16)
> +#define CPUID_EXT3_TCE (1 << 17)
> +#define CPUID_EXT3_NODEID (1 << 19)
> +#define CPUID_EXT3_TBM (1 << 21)
> +#define CPUID_EXT3_TOPOEXT (1 << 22)
> +#define CPUID_EXT3_PERFCORE (1 << 23)
> +#define CPUID_EXT3_PERFNB (1 << 24)
>
> #define CPUID_SVM_NPT (1 << 0)
> #define CPUID_SVM_LBRV (1 << 1)
> @@ -485,7 +496,17 @@
> #define CPUID_SVM_PAUSEFILTER (1 << 10)
> #define CPUID_SVM_PFTHRESHOLD (1 << 12)
>
> +#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
> +#define CPUID_7_0_EBX_BMI1 (1 << 3)
> +#define CPUID_7_0_EBX_HLE (1 << 4)
> +#define CPUID_7_0_EBX_AVX2 (1 << 5)
> #define CPUID_7_0_EBX_SMEP (1 << 7)
> +#define CPUID_7_0_EBX_BMI2 (1 << 8)
> +#define CPUID_7_0_EBX_ERMS (1 << 9)
> +#define CPUID_7_0_EBX_INVPCID (1 << 10)
> +#define CPUID_7_0_EBX_RTM (1 << 11)
> +#define CPUID_7_0_EBX_RDSEED (1 << 18)
> +#define CPUID_7_0_EBX_ADX (1 << 19)
> #define CPUID_7_0_EBX_SMAP (1 << 20)
>
> #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
> --
> 1.7.10.4
>
>
--
Eduardo
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