From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v3 for 1.3 0/3] tcg/arm: misc fixes
Date: Mon, 5 Nov 2012 08:29:42 +0100 [thread overview]
Message-ID: <1352100585-19415-1-git-send-email-aurelien@aurel32.net> (raw)
This patch series fixes the TCG arm backend for the MIPS target, as well
as for big endian targets when not using the ARMv6+ instructions set.
The corresponding patches are candidate for a stable release.
--
Changes v2 -> v3:
- patch 1:
- The new code allow up to 20 bits to be loaded (and not 24 bits).
Change the comments and the assert accordingly.
Changes v1 -> v2:
- patch 1:
- added an assert to make sure the TLB offset fits within 24 bits
- added an assert to make sure both registers are different in ldr_wb
- patches 4 and 5 (optimizations) have been dropped and will be
resubmitted again (when I can find some time to work on them).
Aurelien Jarno (3):
tcg/arm: fix TLB access in qemu-ld/st ops
tcg/arm: fix cross-endian qemu_st16
target-openrisc: remove conflicting definitions from cpu.h
target-openrisc/cpu.h | 18 ---------
tcg/arm/tcg-target.c | 98 ++++++++++++++++++++++++++++++-------------------
2 files changed, 60 insertions(+), 56 deletions(-)
--
1.7.10.4
next reply other threads:[~2012-11-05 7:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-05 7:29 Aurelien Jarno [this message]
2012-11-05 7:29 ` [Qemu-devel] [PATCH v3 for 1.3 1/3] tcg/arm: fix TLB access in qemu-ld/st ops Aurelien Jarno
2012-11-05 7:29 ` [Qemu-devel] [PATCH v3 for 1.3 2/3] tcg/arm: fix cross-endian qemu_st16 Aurelien Jarno
2012-11-05 7:29 ` [Qemu-devel] [PATCH v3 for 1.3 3/3] target-openrisc: remove conflicting definitions from cpu.h Aurelien Jarno
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