From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TVH8E-0005EG-B3 for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:30:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TVH8B-0005A9-Ib for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:30:01 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:49874) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TVH8B-00059p-Bo for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:29:59 -0500 From: Aurelien Jarno Date: Mon, 5 Nov 2012 08:29:42 +0100 Message-Id: <1352100585-19415-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v3 for 1.3 0/3] tcg/arm: misc fixes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno This patch series fixes the TCG arm backend for the MIPS target, as well as for big endian targets when not using the ARMv6+ instructions set. The corresponding patches are candidate for a stable release. -- Changes v2 -> v3: - patch 1: - The new code allow up to 20 bits to be loaded (and not 24 bits). Change the comments and the assert accordingly. Changes v1 -> v2: - patch 1: - added an assert to make sure the TLB offset fits within 24 bits - added an assert to make sure both registers are different in ldr_wb - patches 4 and 5 (optimizations) have been dropped and will be resubmitted again (when I can find some time to work on them). Aurelien Jarno (3): tcg/arm: fix TLB access in qemu-ld/st ops tcg/arm: fix cross-endian qemu_st16 target-openrisc: remove conflicting definitions from cpu.h target-openrisc/cpu.h | 18 --------- tcg/arm/tcg-target.c | 98 ++++++++++++++++++++++++++++++------------------- 2 files changed, 60 insertions(+), 56 deletions(-) -- 1.7.10.4