From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYe74-0001nS-NU for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TYe71-0000Ly-Ld for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:46 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:53226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYe71-0000Km-Eo for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:43 -0500 From: Aurelien Jarno Date: Wed, 14 Nov 2012 15:38:21 +0100 Message-Id: <1352903901-8797-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle Signed-off-by: Aurelien Jarno --- hw/mips_malta.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 0571d58..4d2464a 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) be = 0; #endif /* FPGA */ - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]); + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); -- 1.7.10.4