From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TZJj2-0004zD-GX for qemu-devel@nongnu.org; Fri, 16 Nov 2012 06:04:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TZJiz-0006eh-DQ for qemu-devel@nongnu.org; Fri, 16 Nov 2012 06:04:44 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:35603) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TZJiz-0006cu-6O for qemu-devel@nongnu.org; Fri, 16 Nov 2012 06:04:41 -0500 From: Aurelien Jarno Date: Fri, 16 Nov 2012 12:04:17 +0100 Message-Id: <1353063863-11446-2-git-send-email-aurelien@aurel32.net> In-Reply-To: <1353063863-11446-1-git-send-email-aurelien@aurel32.net> References: <1353063863-11446-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno When rd is 0, which still need to do the actually load to possibly generate a TLB exception. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 01b48fa..c3e00c5 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12631,11 +12631,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, const char *opn = "ldx"; TCGv t0; - if (rd == 0) { - MIPS_DEBUG("NOP"); - return; - } - check_dsp(ctx); t0 = tcg_temp_new(); -- 1.7.10.4