From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP elements
Date: Fri, 16 Nov 2012 12:04:19 +0100 [thread overview]
Message-ID: <1353063863-11446-4-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1353063863-11446-1-git-send-email-aurelien@aurel32.net>
Instead of playing with bit shifting, add two unions (one for 32-bit
values, one for 64-bit ones) to access all the DSP elements with the
correct type.
This make the code easier to read and less error prone, and allow GCC
to vectorize the code in some cases.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/dsp_helper.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c2..8015d8d 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -20,6 +20,28 @@
#include "cpu.h"
#include "helper.h"
+/* As the byte ordering doesn't matter, i.e. all columns are treated
+ identically, these unions can be used directly. */
+typedef union {
+ uint8_t ub[4];
+ int8_t sb[4];
+ uint16_t uh[2];
+ int16_t sh[2];
+ uint32_t uw[1];
+ int32_t sw[1];
+} DSP32Value;
+
+typedef union {
+ uint8_t ub[8];
+ int8_t sb[8];
+ uint16_t uh[4];
+ int16_t sh[4];
+ uint32_t uw[2];
+ int32_t sw[2];
+ uint64_t ul[1];
+ int64_t sl[1];
+} DSP64Value;
+
/*** MIPS DSP internal functions begin ***/
#define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
#define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
--
1.7.10.4
next prev parent reply other threads:[~2012-11-16 11:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-16 11:04 [Qemu-devel] [PATCH 0/7] target-mips: DSP ASE fixes and cleanup Aurelien Jarno
2012-11-16 11:04 ` [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0 Aurelien Jarno
2012-11-21 6:28 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP Aurelien Jarno
2012-11-16 22:02 ` Richard Henderson
2012-11-21 6:51 ` Johnson, Eric
2012-11-16 11:04 ` Aurelien Jarno [this message]
2012-11-21 6:54 ` [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP elements Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 4/7] target-mips: use DSP unions for binary DSP operators Aurelien Jarno
2012-11-16 22:04 ` Richard Henderson
2012-12-05 4:58 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 5/7] target-mips: use DSP unions for unary " Aurelien Jarno
2012-12-05 4:58 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for reduction add instructions Aurelien Jarno
2012-12-05 4:58 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 7/7] target-mips: implement DSP (d)append sub-class with TCG Aurelien Jarno
2012-12-05 4:58 ` Johnson, Eric
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