From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for reduction add instructions
Date: Fri, 16 Nov 2012 12:04:22 +0100 [thread overview]
Message-ID: <1353063863-11446-7-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1353063863-11446-1-git-send-email-aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/dsp_helper.c | 32 +++++++++++++++-----------------
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 3bd2d35..474c249 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -1381,31 +1381,29 @@ target_ulong helper_modsub(target_ulong rs, target_ulong rt)
target_ulong helper_raddu_w_qb(target_ulong rs)
{
- uint8_t rs3, rs2, rs1, rs0;
- uint16_t temp;
-
- MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
-
- temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
+ target_ulong ret = 0;
+ DSP32Value ds;
+ unsigned int i;
- return (target_ulong)temp;
+ ds.uw[0] = rs;
+ for (i = 0 ; i < 4 ; i++) {
+ ret += ds.ub[i];
+ }
+ return ret;
}
#if defined(TARGET_MIPS64)
target_ulong helper_raddu_l_ob(target_ulong rs)
{
- int i;
- uint16_t rs_t[8];
- uint64_t temp;
-
- temp = 0;
+ target_ulong ret = 0;
+ DSP64Value ds;
+ unsigned int i;
- for (i = 0; i < 8; i++) {
- rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
- temp += (uint64_t)rs_t[i];
+ ds.ul[0] = rs;
+ for (i = 0 ; i < 8 ; i++) {
+ ret += ds.ub[i];
}
-
- return temp;
+ return ret;
}
#endif
--
1.7.10.4
next prev parent reply other threads:[~2012-11-16 11:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-16 11:04 [Qemu-devel] [PATCH 0/7] target-mips: DSP ASE fixes and cleanup Aurelien Jarno
2012-11-16 11:04 ` [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0 Aurelien Jarno
2012-11-21 6:28 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP Aurelien Jarno
2012-11-16 22:02 ` Richard Henderson
2012-11-21 6:51 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP elements Aurelien Jarno
2012-11-21 6:54 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 4/7] target-mips: use DSP unions for binary DSP operators Aurelien Jarno
2012-11-16 22:04 ` Richard Henderson
2012-12-05 4:58 ` Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 5/7] target-mips: use DSP unions for unary " Aurelien Jarno
2012-12-05 4:58 ` Johnson, Eric
2012-11-16 11:04 ` Aurelien Jarno [this message]
2012-12-05 4:58 ` [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for reduction add instructions Johnson, Eric
2012-11-16 11:04 ` [Qemu-devel] [PATCH 7/7] target-mips: implement DSP (d)append sub-class with TCG Aurelien Jarno
2012-12-05 4:58 ` Johnson, Eric
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