From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbvUh-00067f-H6 for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TbvUZ-0006it-JN for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:61928) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbvUZ-0006iK-Be for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:35 -0500 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qANFmYk4023467 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 23 Nov 2012 10:48:34 -0500 From: Gerd Hoffmann Date: Fri, 23 Nov 2012 16:48:23 +0100 Message-Id: <1353685711-24573-13-git-send-email-kraxel@redhat.com> In-Reply-To: <1353685711-24573-1-git-send-email-kraxel@redhat.com> References: <1353685711-24573-1-git-send-email-kraxel@redhat.com> Subject: [Qemu-devel] [PATCH 12/20] apci: switch ich9 gpe to memory api List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Gerd Hoffmann Signed-off-by: Gerd Hoffmann --- hw/acpi_ich9.c | 38 ++++++++++++++++++++++++++++---------- hw/acpi_ich9.h | 1 + 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c index 0f025f8..aa290d6 100644 --- a/hw/acpi_ich9.c +++ b/hw/acpi_ich9.c @@ -73,12 +73,7 @@ static void ich9_pm_update_sci_fn(ACPIREGS *regs) static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) { - ICH9LPCPMRegs *pm = opaque; - switch (addr & ICH9_PMIO_MASK) { - case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): - acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); - break; default: break; } @@ -88,13 +83,9 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) static uint32_t pm_ioport_readb(void *opaque, uint32_t addr) { - ICH9LPCPMRegs *pm = opaque; uint32_t val = 0; switch (addr & ICH9_PMIO_MASK) { - case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): - val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr); - break; default: val = 0; break; @@ -209,6 +200,29 @@ static const MemoryRegionOps pm_io_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) +{ + ICH9LPCPMRegs *pm = opaque; + return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); +} + +static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + ICH9LPCPMRegs *pm = opaque; + acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); +} + +static const MemoryRegionOps ich9_gpe_ops = { + .read = ich9_gpe_readb, + .write = ich9_gpe_writeb, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) { ICH9_DEBUG("to 0x%x\n", pm_io_base); @@ -300,8 +314,12 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io); + acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); - acpi_gpe_blk(&pm->acpi_regs, ICH9_PMIO_GPE0_STS); + acpi_gpe_blk(&pm->acpi_regs, 0); + memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0", + ICH9_PMIO_GPE0_LEN); + memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); pm->irq = sci_irq; qemu_register_reset(pm_reset, pm); diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h index 0a2ee6c..f3b05d7 100644 --- a/hw/acpi_ich9.h +++ b/hw/acpi_ich9.h @@ -31,6 +31,7 @@ typedef struct ICH9LPCPMRegs { */ ACPIREGS acpi_regs; MemoryRegion io; + MemoryRegion io_gpe; uint32_t smi_en; uint32_t smi_sts; -- 1.7.1