[Qemu-devel] [PULL for-1.3] QOM CPUState patch queue 2012-11-26

[Qemu-devel] [PULL for-1.3] QOM CPUState patch queue 2012-11-26

[Andreas Färber]

Hello Anthony,

As discussed, here's two bugfixes for x86 CPUs. Please pull for rc1.

Regards,
Andreas

Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>


The following changes since commit cab1e8f3e37d8e883c270e3afd9c7c1c18332f0e:

  Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-11-26 08:19:45 -0600)

are available in the git repository at:


  git://github.com/afaerber/qemu-cpu.git qom-cpu-1.3

for you to fetch changes up to a0a7068104cc9908d0875404b0fa2ebf46e40f97:

  target-i386: Enable SSSE3 TCG support (2012-11-26 17:00:11 +0100)

----------------------------------------------------------------
Aurelien Jarno (1):
      target-i386: Enable SSSE3 TCG support

Eduardo Habkost (1):
      target-i386/cpu: Add missing flags to Haswell CPU model

 target-i386/cpu.c |    7 ++++---
 1 Datei geändert, 4 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)

[Qemu-devel] [PATCH 1/2] target-i386/cpu: Add missing flags to Haswell CPU model

[Andreas Färber]

From: Eduardo Habkost <ehabkost@redhat.com>

When adding the Haswell CPU model, I intended to make it a superset of the
features present on the SandyBridge model, but I have removed the SEP and
RDTSCP features from the feature list by mistake. This patch adds the
missing SEP and RDTSCP features (that are present on SandyBridge) to
Haswell.

Reported-by: Martin Kletzander <mkletzan@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-i386/cpu.c |    5 +++--
 1 Datei geändert, 3 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 64c3491..4fdd4f7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -657,7 +657,7 @@ static x86_def_t builtin_x86_defs[] = {
         .stepping = 1,
         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
-             CPUID_PGE | CPUID_MTRR | CPUID_APIC | CPUID_CX8 |
+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
@@ -666,7 +666,8 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
              CPUID_EXT_PCID,
-        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+             CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
-- 
1.7.10.4

[Qemu-devel] [PATCH 2/2] target-i386: Enable SSSE3 TCG support

[Andreas Färber]

From: Aurelien Jarno <aurelien@aurel32.net>

SSSE3 support has been added to TCG more than 4 years ago in commit
4242b1bd8acc19aaaacffdaad4ac23213d72a72b. It has been disabled by
mistake in commit 551a2dec8fa55006a68393b9d6fb63577d2b3f1c.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-i386/cpu.c |    2 +-
 1 Datei geändert, 1 Zeile hinzugefügt(+), 1 Zeile entfernt(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4fdd4f7..c6c2ca0 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -315,7 +315,7 @@ typedef struct x86_def_t {
           /* missing:
           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
-          CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
+          CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
           CPUID_EXT_HYPERVISOR)
           /* missing:
           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
-- 
1.7.10.4

Re: [Qemu-devel] [PULL for-1.3] QOM CPUState patch queue 2012-11-26

[Anthony Liguori]

Andreas Färber <afaerber@suse.de> writes:

> Hello Anthony,
>
> As discussed, here's two bugfixes for x86 CPUs. Please pull for rc1.
>
> Regards,
> Andreas
>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Aurélien Jarno <aurelien@aurel32.net>
>

Pulled. Thanks.

Regards,

Anthony Liguori

>
> The following changes since commit cab1e8f3e37d8e883c270e3afd9c7c1c18332f0e:
>
>   Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-11-26 08:19:45 -0600)
>
> are available in the git repository at:
>
>
>   git://github.com/afaerber/qemu-cpu.git qom-cpu-1.3
>
> for you to fetch changes up to a0a7068104cc9908d0875404b0fa2ebf46e40f97:
>
>   target-i386: Enable SSSE3 TCG support (2012-11-26 17:00:11 +0100)
>
> ----------------------------------------------------------------
> Aurelien Jarno (1):
>       target-i386: Enable SSSE3 TCG support
>
> Eduardo Habkost (1):
>       target-i386/cpu: Add missing flags to Haswell CPU model
>
>  target-i386/cpu.c |    7 ++++---
>  1 Datei geändert, 4 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)