From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
anthony@codemonkey.ws, "Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH 2/2] target-i386: Enable SSSE3 TCG support
Date: Mon, 26 Nov 2012 17:24:31 +0100 [thread overview]
Message-ID: <1353947071-18478-3-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1353947071-18478-1-git-send-email-afaerber@suse.de>
From: Aurelien Jarno <aurelien@aurel32.net>
SSSE3 support has been added to TCG more than 4 years ago in commit
4242b1bd8acc19aaaacffdaad4ac23213d72a72b. It has been disabled by
mistake in commit 551a2dec8fa55006a68393b9d6fb63577d2b3f1c.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-i386/cpu.c | 2 +-
1 Datei geändert, 1 Zeile hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4fdd4f7..c6c2ca0 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -315,7 +315,7 @@ typedef struct x86_def_t {
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
- CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
+ CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
CPUID_EXT_HYPERVISOR)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
--
1.7.10.4
next prev parent reply other threads:[~2012-11-26 16:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-26 16:24 [Qemu-devel] [PULL for-1.3] QOM CPUState patch queue 2012-11-26 Andreas Färber
2012-11-26 16:24 ` [Qemu-devel] [PATCH 1/2] target-i386/cpu: Add missing flags to Haswell CPU model Andreas Färber
2012-11-26 16:24 ` Andreas Färber [this message]
2012-11-28 21:38 ` [Qemu-devel] [PULL for-1.3] QOM CPUState patch queue 2012-11-26 Anthony Liguori
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