From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdH15-0005l6-0A for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TdH0w-000519-Ko for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56069) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdH0w-00050T-Bu for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:34 -0500 From: Gerd Hoffmann Date: Tue, 27 Nov 2012 09:59:24 +0100 Message-Id: <1354006768-13128-15-git-send-email-kraxel@redhat.com> In-Reply-To: <1354006768-13128-1-git-send-email-kraxel@redhat.com> References: <1354006768-13128-1-git-send-email-kraxel@redhat.com> Subject: [Qemu-devel] [PATCH v2 14/18] apci: switch piix4 gpe to memory api List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: afaerber@suse.de, Gerd Hoffmann Signed-off-by: Gerd Hoffmann --- hw/acpi_piix4.c | 24 ++++++++++++++++++------ 1 files changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index b1d5bf3..c1a58d3 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -57,6 +57,7 @@ struct pci_status { typedef struct PIIX4PMState { PCIDevice dev; MemoryRegion io; + MemoryRegion io_gpe; ACPIREGS ar; APMState apm; @@ -500,7 +501,7 @@ static void piix4_pm_register_types(void) type_init(piix4_pm_register_types) -static uint32_t gpe_readb(void *opaque, uint32_t addr) +static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) { PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); @@ -509,7 +510,8 @@ static uint32_t gpe_readb(void *opaque, uint32_t addr) return val; } -static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) +static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, + unsigned width) { PIIX4PMState *s = opaque; @@ -519,6 +521,16 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); } +static const MemoryRegionOps piix4_gpe_ops = { + .read = gpe_readb, + .write = gpe_writeb, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static uint32_t pci_up_read(void *opaque, uint32_t addr) { PIIX4PMState *s = opaque; @@ -567,10 +579,10 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) { - - register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); - register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); - acpi_gpe_blk(&s->ar, GPE_BASE); + memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0", + GPE_LEN); + memory_region_add_subregion(get_system_io(), GPE_BASE, &s->io_gpe); + acpi_gpe_blk(&s->ar, 0); register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); -- 1.7.1