[Qemu-devel] [PATCH 0/3] ARM: fix secondary boot GIC init, GIC bugs

[Peter Maydell <peter.maydell@linaro.org>]

The secondary CPU boot code we use on ARM had a couple of
places where it was accidentally relying on bugs or implementation
dependent behaviour of QEMU's on GIC implementation:
 * we weren't initialising the GICC_PMR priority mask, which
   in a correct v1 or v2 GIC is set to mask out all interrupts
   from reset. This worked on the QEMU GIC because our GIC (a)
   gets the reset value of PMR wrong on non-11MPCore and (b) is
   doing an incorrect comparison against the PMR value when
   delivering interrupts anyway.
 * no barrier between initialising the GIC and doing a WFI; this
   is fine for TCG QEMU but could potentially result in the GIC
   config not being guaranteed to have happened before we hit the
   WFI when running on real CPU hardware under ARM KVM.

This patch series first fixes the secondary CPU boot code bugs,
and then corrects our GIC model to match the specs.

NB: I don't have a working test setup/images for highbank or
exynos4 so those changes are only compile tested, but they are
basically the same as the generic boot code changes.

Peter Maydell (3):
  hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init
  hw/arm_gic: Fix comparison with priority mask register
  hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs

 hw/arm_boot.c       |   17 ++++++++++++++---
 hw/arm_gic.c        |    2 +-
 hw/arm_gic_common.c |    6 +++++-
 hw/armv7m_nvic.c    |    4 +++-
 hw/exynos4210.c     |   10 +++++++---
 hw/highbank.c       |    7 +++++--
 6 files changed, 35 insertions(+), 11 deletions(-)

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1.7.9.5