From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Te7W5-0005B4-D0 for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:03:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Te7Vz-0002Dj-0t for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:03:13 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:60606 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Te7Vy-0002Bi-Q6 for qemu-devel@nongnu.org; Thu, 29 Nov 2012 12:03:06 -0500 From: Peter Maydell Date: Thu, 29 Nov 2012 17:02:57 +0000 Message-Id: <1354208577-8935-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> References: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/3] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , patches@linaro.org, Marc Zyngier , Dmitry Solodkiy , Maksim Kozlov , kvmarm@lists.cs.columbia.edu The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell --- hw/arm_gic_common.c | 6 +++++- hw/armv7m_nvic.c | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 8369309..73ae331 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev) int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { - s->priority_mask[i] = 0xf0; + if (s->revision == REV_11MPCORE) { + s->priority_mask[i] = 0xf0; + } else { + s->priority_mask[i] = 0; + } s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index f0a2e7b..4963678 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -455,9 +455,11 @@ static void armv7m_nvic_reset(DeviceState *dev) nc->parent_reset(dev); /* Common GIC reset resets to disabled; the NVIC doesn't have * per-CPU interfaces so mark our non-existent CPU interface - * as enabled by default. + * as enabled by default, and with a priority mask which allows + * all interrupts through. */ s->gic.cpu_enabled[0] = 1; + s->gic.priority_mask[0] = 0x100; /* The NVIC as a whole is always enabled. */ s->gic.enabled = 1; systick_reset(s); -- 1.7.9.5