From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tfvfb-0003B4-BU for qemu-devel@nongnu.org; Tue, 04 Dec 2012 11:48:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TfvfW-0005qm-Jn for qemu-devel@nongnu.org; Tue, 04 Dec 2012 11:48:31 -0500 Received: from cantor2.suse.de ([195.135.220.15]:33219 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TfvfW-0005qh-6x for qemu-devel@nongnu.org; Tue, 04 Dec 2012 11:48:26 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 4 Dec 2012 17:48:16 +0100 Message-Id: <1354639696-22168-7-git-send-email-afaerber@suse.de> In-Reply-To: <1354639696-22168-1-git-send-email-afaerber@suse.de> References: <1354639696-22168-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 6/6] hw/dma.c: Replace register_ioport_* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Julien Grall , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Julien Grall Replace all register_ioport_*() with the new Memory API functions. This permits to use the new Memory stuff like listeners. Signed-off-by: Julien Grall Acked-by: Avi Kivity [AF: Rebased onto hwaddr] Signed-off-by: Andreas F=C3=A4rber --- hw/dma.c | 106 +++++++++++++++++++++++++++++++++++++++++---------------= ------ 1 Datei ge=C3=A4ndert, 70 Zeilen hinzugef=C3=BCgt(+), 36 Zeilen entfernt= (-) diff --git a/hw/dma.c b/hw/dma.c index d6aeac2..c2d7b21 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -58,6 +58,8 @@ static struct dma_cont { int dshift; struct dma_regs regs[4]; qemu_irq *cpu_request_exit; + MemoryRegion channel_io; + MemoryRegion cont_io; } dma_controllers[2]; =20 enum { @@ -149,7 +151,7 @@ static inline int getff (struct dma_cont *d) return ff; } =20 -static uint32_t read_chan (void *opaque, uint32_t nport) +static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) { struct dma_cont *d =3D opaque; int ichan, nreg, iport, ff, val, dir; @@ -171,7 +173,8 @@ static uint32_t read_chan (void *opaque, uint32_t npo= rt) return (val >> (d->dshift + (ff << 3))) & 0xff; } =20 -static void write_chan (void *opaque, uint32_t nport, uint32_t data) +static void write_chan(void *opaque, hwaddr nport, uint64_t data, + unsigned size) { struct dma_cont *d =3D opaque; int iport, ichan, nreg; @@ -189,22 +192,23 @@ static void write_chan (void *opaque, uint32_t npor= t, uint32_t data) } } =20 -static void write_cont (void *opaque, uint32_t nport, uint32_t data) +static void write_cont(void *opaque, hwaddr nport, uint64_t data, + unsigned size) { struct dma_cont *d =3D opaque; int iport, ichan =3D 0; =20 iport =3D (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x08: /* command */ + case 0x01: /* command */ if ((data !=3D 0) && (data & CMD_NOT_SUPPORTED)) { - dolog ("command %#x not supported\n", data); + dolog("command %"PRIx64" not supported\n", data); return; } d->command =3D data; break; =20 - case 0x09: + case 0x02: ichan =3D data & 3; if (data & 4) { d->status |=3D 1 << (ichan + 4); @@ -216,7 +220,7 @@ static void write_cont (void *opaque, uint32_t nport,= uint32_t data) DMA_run(); break; =20 - case 0x0a: /* single mask */ + case 0x03: /* single mask */ if (data & 4) d->mask |=3D 1 << (data & 3); else @@ -224,7 +228,7 @@ static void write_cont (void *opaque, uint32_t nport,= uint32_t data) DMA_run(); break; =20 - case 0x0b: /* mode */ + case 0x04: /* mode */ { ichan =3D data & 3; #ifdef DEBUG_DMA @@ -243,23 +247,23 @@ static void write_cont (void *opaque, uint32_t npor= t, uint32_t data) break; } =20 - case 0x0c: /* clear flip flop */ + case 0x05: /* clear flip flop */ d->flip_flop =3D 0; break; =20 - case 0x0d: /* reset */ + case 0x06: /* reset */ d->flip_flop =3D 0; d->mask =3D ~0; d->status =3D 0; d->command =3D 0; break; =20 - case 0x0e: /* clear mask for all channels */ + case 0x07: /* clear mask for all channels */ d->mask =3D 0; DMA_run(); break; =20 - case 0x0f: /* write mask for all channels */ + case 0x08: /* write mask for all channels */ d->mask =3D data; DMA_run(); break; @@ -277,7 +281,7 @@ static void write_cont (void *opaque, uint32_t nport,= uint32_t data) #endif } =20 -static uint32_t read_cont (void *opaque, uint32_t nport) +static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) { struct dma_cont *d =3D opaque; int iport, val; @@ -463,7 +467,7 @@ void DMA_schedule(int nchan) static void dma_reset(void *opaque) { struct dma_cont *d =3D opaque; - write_cont (d, (0x0d << d->dshift), 0); + write_cont(d, (0x06 << d->dshift), 0, 1); } =20 static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int = dma_len) @@ -473,38 +477,68 @@ static int dma_phony_handler (void *opaque, int nch= an, int dma_pos, int dma_len) return dma_pos; } =20 + +static const MemoryRegionOps channel_io_ops =3D { + .read =3D read_chan, + .write =3D write_chan, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +/* IOport from page_base */ +static const MemoryRegionPortio page_portio_list[] =3D { + { 0x01, 3, 1, .write =3D write_page, .read =3D read_page, }, + { 0x07, 1, 1, .write =3D write_page, .read =3D read_page, }, + PORTIO_END_OF_LIST(), +}; + +/* IOport from pageh_base */ +static const MemoryRegionPortio pageh_portio_list[] =3D { + { 0x01, 3, 1, .write =3D write_pageh, .read =3D read_pageh, }, + { 0x07, 3, 1, .write =3D write_pageh, .read =3D read_pageh, }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps cont_io_ops =3D { + .read =3D read_cont, + .write =3D write_cont, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + /* dshift =3D 0: 8 bit DMA, 1 =3D 16 bit DMA */ static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base, int pageh_base, qemu_irq *cpu_request_exit) { - static const int page_port_list[] =3D { 0x1, 0x2, 0x3, 0x7 }; int i; =20 d->dshift =3D dshift; d->cpu_request_exit =3D cpu_request_exit; - for (i =3D 0; i < 8; i++) { - register_ioport_write (base + (i << dshift), 1, 1, write_chan, d= ); - register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); - } - for (i =3D 0; i < ARRAY_SIZE (page_port_list); i++) { - register_ioport_write (page_base + page_port_list[i], 1, 1, - write_page, d); - register_ioport_read (page_base + page_port_list[i], 1, 1, - read_page, d); - if (pageh_base >=3D 0) { - register_ioport_write (pageh_base + page_port_list[i], 1, 1, - write_pageh, d); - register_ioport_read (pageh_base + page_port_list[i], 1, 1, - read_pageh, d); - } - } - for (i =3D 0; i < 8; i++) { - register_ioport_write (base + ((i + 8) << dshift), 1, 1, - write_cont, d); - register_ioport_read (base + ((i + 8) << dshift), 1, 1, - read_cont, d); + + memory_region_init_io(&d->channel_io, &channel_io_ops, d, + "dma-chan", 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(NULL), + base, &d->channel_io); + + isa_register_portio_list(NULL, page_base, page_portio_list, d, + "dma-page"); + if (pageh_base >=3D 0) { + isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, + "dma-pageh"); } + + memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont", + 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(NULL), + base + (8 << d->dshift), &d->cont_io); + qemu_register_reset(dma_reset, d); dma_reset(d); for (i =3D 0; i < ARRAY_SIZE (d->regs); ++i) { --=20 1.7.10.4