From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg5Sg-0006Sw-4Q for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tg5Se-00029B-Tr for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:49 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:39861) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg5Se-00021d-F7 for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:48 -0500 Received: by mail-la0-f45.google.com with SMTP id p9so3416568laa.4 for ; Tue, 04 Dec 2012 19:15:47 -0800 (PST) From: Max Filippov Date: Wed, 5 Dec 2012 07:15:24 +0400 Message-Id: <1354677327-22552-6-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1354677327-22552-1-git-send-email-jcmvbkbc@gmail.com> References: <1354677327-22552-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 5/8] target-xtensa: implement MISC SR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Max Filippov The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 1 + target-xtensa/overlay_tool.h | 1 + target-xtensa/translate.c | 4 ++++ 3 files changed, 6 insertions(+), 0 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a73d32d..08fd5bc 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -153,6 +153,7 @@ enum { ICOUNTLEVEL = 237, EXCVADDR = 238, CCOMPARE = 240, + MISC = 244, }; #define PS_INTLEVEL 0xf diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index 0b47029..dd4f51a 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -95,6 +95,7 @@ /* Other, TODO */ \ XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ + XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID)) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fbeac7f..48a22de 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -179,6 +179,10 @@ static const XtensaReg sregnames[256] = { XTENSA_OPTION_TIMER_INTERRUPT), [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", XTENSA_OPTION_TIMER_INTERRUPT), + [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), + [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), + [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), + [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), }; static const XtensaReg uregnames[256] = { -- 1.7.7.6