From: Alexander Graf <agraf@suse.de>
To: "qemu-ppc@nongnu.org List" <qemu-ppc@nongnu.org>
Cc: qemu-devel qemu-devel <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [PATCH 03/19] openpic: update to proper memory api
Date: Sat, 8 Dec 2012 14:44:26 +0100 [thread overview]
Message-ID: <1354974282-1915-4-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1354974282-1915-1-git-send-email-agraf@suse.de>
The openpic code was still using the old mmio memory api. Convert it to
be a generic memory api user and clean up some code that becomes redundant
that way.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/openpic.c | 138 ++++++++++++++++++++--------------------------------------
1 files changed, 48 insertions(+), 90 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 0d858cc..2776a36 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -460,7 +460,8 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
opp->src[n_IRQ].ipvp);
}
-static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
+static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
@@ -526,7 +527,7 @@ static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
}
}
-static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
+static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -583,7 +584,8 @@ static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
return retval;
}
-static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
int idx;
@@ -614,7 +616,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
+static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -647,7 +649,8 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
return retval;
}
-static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
int idx;
@@ -666,7 +669,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t openpic_src_read (void *opaque, uint32_t addr)
+static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -748,7 +751,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
}
}
-static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
+static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
@@ -832,96 +836,63 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
return retval;
}
-static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
+static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
-static void openpic_buggy_write (void *opaque,
- hwaddr addr, uint32_t val)
-{
- printf("Invalid OPENPIC write access !\n");
-}
-
-static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
-{
- printf("Invalid OPENPIC read access !\n");
-
- return -1;
-}
-
-static void openpic_writel (void *opaque,
- hwaddr addr, uint32_t val)
+static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *opp = opaque;
- addr &= 0x3FFFF;
DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
if (addr < 0x1100) {
/* Global registers */
- openpic_gbl_write(opp, addr, val);
+ openpic_gbl_write(opp, addr, val, len);
} else if (addr < 0x10000) {
/* Timers registers */
- openpic_timer_write(opp, addr, val);
+ openpic_timer_write(opp, addr, val, len);
} else if (addr < 0x20000) {
/* Source registers */
- openpic_src_write(opp, addr, val);
+ openpic_src_write(opp, addr, val, len);
} else {
/* CPU registers */
- openpic_cpu_write(opp, addr, val);
+ openpic_cpu_write(opp, addr, val, len);
}
}
-static uint32_t openpic_readl (void *opaque,hwaddr addr)
+static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *opp = opaque;
uint32_t retval;
- addr &= 0x3FFFF;
DPRINTF("%s: offset %08x\n", __func__, (int)addr);
if (addr < 0x1100) {
/* Global registers */
- retval = openpic_gbl_read(opp, addr);
+ retval = openpic_gbl_read(opp, addr, len);
} else if (addr < 0x10000) {
/* Timers registers */
- retval = openpic_timer_read(opp, addr);
+ retval = openpic_timer_read(opp, addr, len);
} else if (addr < 0x20000) {
/* Source registers */
- retval = openpic_src_read(opp, addr);
+ retval = openpic_src_read(opp, addr, len);
} else {
/* CPU registers */
- retval = openpic_cpu_read(opp, addr);
+ retval = openpic_cpu_read(opp, addr, len);
}
return retval;
}
-static uint64_t openpic_read(void *opaque, hwaddr addr,
- unsigned size)
-{
- openpic_t *opp = opaque;
-
- switch (size) {
- case 4: return openpic_readl(opp, addr);
- default: return openpic_buggy_read(opp, addr);
- }
-}
-
-static void openpic_write(void *opaque, hwaddr addr,
- uint64_t data, unsigned size)
-{
- openpic_t *opp = opaque;
-
- switch (size) {
- case 4: return openpic_writel(opp, addr, data);
- default: return openpic_buggy_write(opp, addr, data);
- }
-}
-
static const MemoryRegionOps openpic_ops = {
.read = openpic_read,
.write = openpic_write,
.endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
@@ -1130,7 +1101,8 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x00000000;
}
-static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
+static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned len)
{
openpic_t *mpp = opaque;
int idx, cpu;
@@ -1138,7 +1110,6 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- addr &= 0xFFFF;
cpu = addr >> 12;
idx = (addr >> 6) & 0x3;
switch (addr & 0x30) {
@@ -1163,7 +1134,7 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
}
}
-static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
+static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1173,7 +1144,6 @@ static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
- addr &= 0xFFFF;
cpu = addr >> 12;
idx = (addr >> 6) & 0x3;
switch (addr & 0x30) {
@@ -1241,45 +1211,33 @@ static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
}
static const MemoryRegionOps mpic_glb_ops = {
- .old_mmio = {
- .write = { openpic_buggy_write,
- openpic_buggy_write,
- openpic_gbl_write,
- },
- .read = { openpic_buggy_read,
- openpic_buggy_read,
- openpic_gbl_read,
- },
- },
+ .write = openpic_gbl_write,
+ .read = openpic_gbl_read,
.endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static const MemoryRegionOps mpic_tmr_ops = {
- .old_mmio = {
- .write = { openpic_buggy_write,
- openpic_buggy_write,
- mpic_timer_write,
- },
- .read = { openpic_buggy_read,
- openpic_buggy_read,
- mpic_timer_read,
- },
- },
+ .write = mpic_timer_write,
+ .read = mpic_timer_read,
.endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static const MemoryRegionOps mpic_cpu_ops = {
- .old_mmio = {
- .write = { openpic_buggy_write,
- openpic_buggy_write,
- openpic_cpu_write,
- },
- .read = { openpic_buggy_read,
- openpic_buggy_read,
- openpic_cpu_read,
- },
- },
+ .write = openpic_cpu_write,
+ .read = openpic_cpu_read,
.endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static const MemoryRegionOps mpic_irq_ops = {
--
1.6.0.2
next prev parent reply other threads:[~2012-12-08 13:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-08 13:44 [Qemu-devel] [PATCH 00/19] OpenPIC refactoring and MSI support Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 01/19] openpic: Remove unused code Alexander Graf
2012-12-08 15:12 ` Andreas Färber
2012-12-08 15:14 ` Alexander Graf
2012-12-08 17:06 ` Hervé Poussineau
2012-12-08 13:44 ` [Qemu-devel] [PATCH 02/19] mpic: Unify numbering scheme Alexander Graf
2012-12-10 23:34 ` [Qemu-devel] [Qemu-ppc] " Scott Wood
2012-12-10 23:40 ` Scott Wood
2012-12-11 8:14 ` Alexander Graf
2012-12-11 17:39 ` Scott Wood
2012-12-08 13:44 ` Alexander Graf [this message]
2012-12-08 13:44 ` [Qemu-devel] [PATCH 04/19] openpic: combine mpic and openpic src handlers Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 05/19] openpic: Convert subregions to memory api Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 06/19] openpic: combine mpic and openpic irq raise functions Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 07/19] openpic: merge mpic and openpic timer handling Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 08/19] openpic: combine openpic and mpic reset functions Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 09/19] openpic: unify memory api subregions Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 10/19] openpic: remove unused type variable Alexander Graf
2012-12-10 23:42 ` [Qemu-devel] [Qemu-ppc] " Scott Wood
2012-12-11 8:17 ` Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 11/19] openpic: convert simple reg operations to builtin bitops Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 12/19] openpic: rename openpic_t to OpenPICState Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 13/19] openpic: remove irq_out Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 14/19] openpic: convert to qdev Alexander Graf
2012-12-10 23:47 ` Scott Wood
2012-12-11 8:25 ` Alexander Graf
2012-12-11 17:47 ` Scott Wood
2012-12-12 0:56 ` Alexander Graf
2012-12-12 1:38 ` Scott Wood
2012-12-12 10:37 ` Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 15/19] openpic: make brr1 model specific Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 16/19] openpic: add Shared MSI support Alexander Graf
2012-12-11 0:36 ` [Qemu-devel] [Qemu-ppc] " Scott Wood
2012-12-11 8:10 ` Alexander Graf
2012-12-11 17:35 ` Scott Wood
2012-12-12 0:53 ` Alexander Graf
2012-12-12 1:42 ` Scott Wood
2012-12-12 11:12 ` Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 17/19] PPC: e500: Add " Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 18/19] PPC: e500: Declare pci bridge as bridge Alexander Graf
2012-12-08 13:44 ` [Qemu-devel] [PATCH 19/19] MSI-X: Fix endianness Alexander Graf
2012-12-08 22:41 ` Michael S. Tsirkin
-- strict thread matches above, loose matches on Subject: below --
2012-12-12 14:12 [Qemu-devel] [PATCH 00/19] OpenPIC refactoring and MSI support v2 Alexander Graf
2012-12-12 14:12 ` [Qemu-devel] [PATCH 03/19] openpic: update to proper memory api Alexander Graf
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