From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThuA9-0001Pt-Nl for qemu-devel@nongnu.org; Sun, 09 Dec 2012 22:36:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ThuA5-0007Im-Hy for qemu-devel@nongnu.org; Sun, 09 Dec 2012 22:36:13 -0500 Received: from vega.ertl.jp ([133.6.204.129]:39924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThuA5-0007I4-96 for qemu-devel@nongnu.org; Sun, 09 Dec 2012 22:36:09 -0500 From: dsl@ertl.jp Date: Mon, 10 Dec 2012 12:32:47 +0900 Message-Id: <1355110367-12028-1-git-send-email-dsl@ertl.jp> Subject: [Qemu-devel] [PATCH] target-arm: fix target CPUs on ARM GIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, paul@codesourcery.com, Daniel Sangorrin Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: Daniel Sangorrin --- hw/arm_gic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f9e423f..97b0677 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -374,7 +374,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, value = 0xff; for (i = 0; i < 8; i++) { if (value & (1 << i)) { - int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); + int mask = + (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; if (!GIC_TEST_ENABLED(irq + i, cm)) { @@ -417,7 +418,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, for (i = 0; i < 8; i++) { if (value & (1 << i)) { - GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); + GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); } } } else if (offset < 0x300) { -- 1.7.9.5