From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TiRfl-00014Y-Cc for qemu-devel@nongnu.org; Tue, 11 Dec 2012 10:23:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TiRfY-0000Ry-Ta for qemu-devel@nongnu.org; Tue, 11 Dec 2012 10:23:05 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:55594 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TiRfY-0000Pc-O2 for qemu-devel@nongnu.org; Tue, 11 Dec 2012 10:22:52 -0500 From: Peter Maydell Date: Tue, 11 Dec 2012 15:22:36 +0000 Message-Id: <1355239360-29249-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1355239360-29249-1-git-send-email-peter.maydell@linaro.org> References: <1355239360-29249-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/6] hw/arm_gic: Fix comparison with priority mask register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Paul Brook The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: Peter Maydell Reviewed-by: Igor Mitsyanko --- hw/arm_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f9e423f..672d539 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -73,7 +73,7 @@ void gic_update(GICState *s) } } level = 0; - if (best_prio <= s->priority_mask[cpu]) { + if (best_prio < s->priority_mask[cpu]) { s->current_pending[cpu] = best_irq; if (best_prio < s->running_priority[cpu]) { DPRINTF("Raised pending IRQ %d\n", best_irq); -- 1.7.9.5