From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tl3NK-0005HG-2k for qemu-devel@nongnu.org; Tue, 18 Dec 2012 15:02:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tl3NH-0000cy-82 for qemu-devel@nongnu.org; Tue, 18 Dec 2012 15:02:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36541) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tl3NH-0000cA-0C for qemu-devel@nongnu.org; Tue, 18 Dec 2012 15:02:47 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qBIK2kUQ005319 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 18 Dec 2012 15:02:46 -0500 Received: from blackpad.lan.raisama.net (vpn1-6-125.gru2.redhat.com [10.97.6.125]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id qBIK2jiW020079 for ; Tue, 18 Dec 2012 15:02:46 -0500 From: Eduardo Habkost Date: Tue, 18 Dec 2012 18:04:04 -0200 Message-Id: <1355861053-11460-12-git-send-email-ehabkost@redhat.com> In-Reply-To: <1355861053-11460-1-git-send-email-ehabkost@redhat.com> References: <1355861053-11460-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [RFC 11/20] target-openrisc: implement CPU realize() method List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Eduardo Habkost --- target-openrisc/cpu.c | 19 ++++++++++++++----- target-openrisc/cpu.h | 1 - 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index e152a3a..0a8253e 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "qemu-common.h" +#include "qemu-error.h" /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) @@ -62,12 +63,12 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature) cpu->env.cpucfgr = cpu->feature; } -void openrisc_cpu_realize(Object *obj, Error **errp) +static void openrisc_cpu_realize(CPUState *cpu, Error **errp) { - OpenRISCCPU *cpu = OPENRISC_CPU(obj); + OpenRISCCPU *oc = OPENRISC_CPU(cpu); - qemu_init_vcpu(&cpu->env); - cpu_reset(CPU(cpu)); + qemu_init_vcpu(&oc->env); + cpu_reset(cpu); } static void openrisc_cpu_initfn(Object *obj) @@ -120,6 +121,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) occ->parent_reset = cc->reset; cc->reset = openrisc_cpu_reset; + cc->realize = openrisc_cpu_realize; } static void cpu_register(const OpenRISCCPUInfo *info) @@ -158,6 +160,7 @@ static void openrisc_cpu_register_types(void) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) { OpenRISCCPU *cpu; + Error *err = NULL; if (!object_class_by_name(cpu_model)) { return NULL; @@ -165,9 +168,15 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) cpu = OPENRISC_CPU(object_new(cpu_model)); CPU(cpu)->cpu_model_str = cpu_model; - openrisc_cpu_realize(OBJECT(cpu), NULL); + cpu_realize(CPU(cpu), &err); + if (err) { + goto error; + } return cpu; +error: + error_report("cpu_openrisc_init: %s", error_get_pretty(err)); + return NULL; } typedef struct OpenRISCCPUList { diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index d7470a9..d0a2fdc 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -347,7 +347,6 @@ static inline CPUOpenRISCState *openrisc_cpu_get_env(OpenRISCCPU *cpu) #define CPU_GET_ENV(cpu) openrisc_cpu_get_env(OPENRISC_CPU(cpu)) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); -void openrisc_cpu_realize(Object *obj, Error **errp); void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); int cpu_openrisc_exec(CPUOpenRISCState *s); -- 1.7.11.7