From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH 12/20] ppc: Pass PowerPCCPU to ppc_set_irq()
Date: Wed, 19 Dec 2012 14:36:28 +0100 [thread overview]
Message-ID: <1355924196-19288-13-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1355924196-19288-1-git-send-email-afaerber@suse.de>
Adapt static caller functions.
This cleans up after passing PowerPCCPU to kvmppc_set_interrupt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/ppc.c | 66 ++++++++++++++++++++++++++++++++++----------------------
hw/ppc.h | 2 +-
hw/ppc_booke.c | 28 ++++++++++++++++--------
3 Dateien geändert, 60 Zeilen hinzugefügt(+), 36 Zeilen entfernt(-)
diff --git a/hw/ppc.c b/hw/ppc.c
index e99a93d..6db595f 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -50,8 +50,9 @@
static void cpu_ppc_tb_stop (CPUPPCState *env);
static void cpu_ppc_tb_start (CPUPPCState *env);
-void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
+void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
{
+ CPUPPCState *env = &cpu->env;
unsigned int old_pending = env->pending_interrupts;
if (level) {
@@ -65,7 +66,7 @@ void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
if (old_pending != env->pending_interrupts) {
#ifdef CONFIG_KVM
- kvmppc_set_interrupt(ppc_env_get_cpu(env), n_IRQ, level);
+ kvmppc_set_interrupt(cpu, n_IRQ, level);
#endif
}
@@ -100,13 +101,13 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active high */
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
break;
case PPC6xx_INPUT_SMI:
/* Level sensitive - active high */
LOG_IRQ("%s: set the SMI IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
break;
case PPC6xx_INPUT_MCP:
/* Negative edge sensitive */
@@ -116,7 +117,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
if (cur_level == 1 && level == 0) {
LOG_IRQ("%s: raise machine check state\n",
__func__);
- ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
+ ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
}
break;
case PPC6xx_INPUT_CKSTP_IN:
@@ -138,7 +139,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
case PPC6xx_INPUT_SRESET:
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
break;
default:
/* Unknown pin - do nothing */
@@ -178,13 +179,13 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active high */
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
break;
case PPC970_INPUT_THINT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
level);
- ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
break;
case PPC970_INPUT_MCP:
/* Negative edge sensitive */
@@ -194,7 +195,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
if (cur_level == 1 && level == 0) {
LOG_IRQ("%s: raise machine check state\n",
__func__);
- ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
+ ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
}
break;
case PPC970_INPUT_CKSTP:
@@ -218,7 +219,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
case PPC970_INPUT_SRESET:
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
break;
case PPC970_INPUT_TBEN:
LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
@@ -259,7 +260,7 @@ static void power7_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active high */
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
break;
default:
/* Unknown pin - do nothing */
@@ -319,13 +320,13 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active high */
LOG_IRQ("%s: set the critical IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
break;
case PPC40x_INPUT_INT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
break;
case PPC40x_INPUT_HALT:
/* Level sensitive - active low */
@@ -342,7 +343,7 @@ static void ppc40x_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active high */
LOG_IRQ("%s: set the debug pin state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
@@ -387,26 +388,26 @@ static void ppce500_set_irq(void *opaque, int pin, int level)
case PPCE500_INPUT_RESET_CORE:
if (level) {
LOG_IRQ("%s: reset the PowerPC core\n", __func__);
- ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
}
break;
case PPCE500_INPUT_CINT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the critical IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
break;
case PPCE500_INPUT_INT:
/* Level sensitive - active high */
LOG_IRQ("%s: set the core IRQ state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
break;
case PPCE500_INPUT_DEBUG:
/* Level sensitive - active high */
LOG_IRQ("%s: set the debug pin state to %d\n",
__func__, level);
- ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
+ ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
@@ -645,16 +646,20 @@ uint64_t cpu_ppc_load_purr (CPUPPCState *env)
*/
static inline void cpu_ppc_decr_excp(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
/* Raise it */
LOG_TB("raise decrementer exception\n");
- ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
+ ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
}
static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
/* Raise it */
LOG_TB("raise decrementer exception\n");
- ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
+ ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
}
static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,
@@ -829,12 +834,14 @@ struct ppc40x_timer_t {
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
env = opaque;
+ cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_get_clock_ns(vm_clock);
@@ -860,8 +867,9 @@ static void cpu_4xx_fit_cb (void *opaque)
next++;
qemu_mod_timer(ppc40x_timer->fit_timer, next);
env->spr[SPR_40x_TSR] |= 1 << 26;
- if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
- ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
+ if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
+ ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
+ }
LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
@@ -897,16 +905,19 @@ static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
static void cpu_4xx_pit_cb (void *opaque)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
env = opaque;
+ cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
env->spr[SPR_40x_TSR] |= 1 << 27;
- if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
- ppc_set_irq(env, ppc40x_timer->decr_excp, 1);
+ if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
+ ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
+ }
start_stop_pit(env, tb_env, 1);
LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
"%016" PRIx64 "\n", __func__,
@@ -919,12 +930,14 @@ static void cpu_4xx_pit_cb (void *opaque)
/* Watchdog timer */
static void cpu_4xx_wdt_cb (void *opaque)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
env = opaque;
+ cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_get_clock_ns(vm_clock);
@@ -961,8 +974,9 @@ static void cpu_4xx_wdt_cb (void *opaque)
qemu_mod_timer(ppc40x_timer->wdt_timer, next);
ppc40x_timer->wdt_next = next;
env->spr[SPR_40x_TSR] |= 1 << 30;
- if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
- ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
+ if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
+ ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
+ }
break;
case 0x3:
env->spr[SPR_40x_TSR] &= ~0x30000000;
diff --git a/hw/ppc.h b/hw/ppc.h
index 2f3ea27..64463ad 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -1,4 +1,4 @@
-void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
+void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c
index d51e7fa..da6bc4a 100644
--- a/hw/ppc_booke.c
+++ b/hw/ppc_booke.c
@@ -71,17 +71,19 @@ struct booke_timer_t {
uint32_t flags;
};
-static void booke_update_irq(CPUPPCState *env)
+static void booke_update_irq(PowerPCCPU *cpu)
{
- ppc_set_irq(env, PPC_INTERRUPT_DECR,
+ CPUPPCState *env = &cpu->env;
+
+ ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
(env->spr[SPR_BOOKE_TSR] & TSR_DIS
&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
- ppc_set_irq(env, PPC_INTERRUPT_WDT,
+ ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
(env->spr[SPR_BOOKE_TSR] & TSR_WIS
&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
- ppc_set_irq(env, PPC_INTERRUPT_FIT,
+ ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
(env->spr[SPR_BOOKE_TSR] & TSR_FIS
&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
}
@@ -154,9 +156,10 @@ static void booke_update_fixed_timer(CPUPPCState *env,
static void booke_decr_cb(void *opaque)
{
CPUPPCState *env = opaque;
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
- booke_update_irq(env);
+ booke_update_irq(cpu);
if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
/* Auto Reload */
@@ -166,16 +169,18 @@ static void booke_decr_cb(void *opaque)
static void booke_fit_cb(void *opaque)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
env = opaque;
+ cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
booke_timer = tb_env->opaque;
env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
- booke_update_irq(env);
+ booke_update_irq(cpu);
booke_update_fixed_timer(env,
booke_get_fit_target(env, tb_env),
@@ -185,17 +190,19 @@ static void booke_fit_cb(void *opaque)
static void booke_wdt_cb(void *opaque)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
env = opaque;
+ cpu = ppc_env_get_cpu(env);
tb_env = env->tb_env;
booke_timer = tb_env->opaque;
/* TODO: There's lots of complicated stuff to do here */
- booke_update_irq(env);
+ booke_update_irq(cpu);
booke_update_fixed_timer(env,
booke_get_wdt_target(env, tb_env),
@@ -205,19 +212,22 @@ static void booke_wdt_cb(void *opaque)
void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
env->spr[SPR_BOOKE_TSR] &= ~val;
- booke_update_irq(env);
+ booke_update_irq(cpu);
}
void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc_tb_t *tb_env = env->tb_env;
booke_timer_t *booke_timer = tb_env->opaque;
tb_env = env->tb_env;
env->spr[SPR_BOOKE_TCR] = val;
- booke_update_irq(env);
+ booke_update_irq(cpu);
booke_update_fixed_timer(env,
booke_get_fit_target(env, tb_env),
--
1.7.10.4
next prev parent reply other threads:[~2012-12-19 13:37 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-19 13:36 [Qemu-devel] [PULL] QOM CPUState patch queue 2012-12-19 Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 01/20] target-alpha: Let cpu_alpha_init() return AlphaCPU Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 02/20] alpha: Pass AlphaCPU array to Typhoon Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 03/20] target-alpha: Avoid leaking the alarm timer over reset Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 04/20] target-alpha: Turn CPU definitions into subclasses Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 05/20] target-alpha: Add support for -cpu ? Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 06/20] cpu: Introduce CPUListState struct Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 07/20] qdev: Coding style fixes Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 08/20] qdev-properties.c: Separate core from the code used only by qemu-system-* Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 09/20] cpu: Move kvm_fd into CPUState Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 10/20] kvm: Pass CPUState to kvm_arch_* Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 11/20] kvm: Pass CPUState to kvm_vcpu_ioctl() Andreas Färber
2012-12-19 13:36 ` Andreas Färber [this message]
2012-12-19 13:36 ` [Qemu-devel] [PATCH 13/20] ppc: Pass PowerPCCPU to [h]decr callbacks Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 14/20] ppc: Pass PowerPCCPU to [h]decr timer callbacks Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 15/20] ppc_booke: Pass PowerPCCPU to {decr, fit, wdt} " Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 16/20] ppc4xx_devs: Return PowerPCCPU from ppc4xx_init() Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 17/20] ppc_booke: Pass PowerPCCPU to ppc_booke_timers_init() Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 18/20] cpu: Move kvm_state field into CPUState Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 19/20] cpu: Move kvm_run " Andreas Färber
2012-12-19 13:36 ` [Qemu-devel] [PATCH 20/20] MAINTAINERS: Include X86CPU in CPU maintenance area Andreas Färber
2012-12-22 12:08 ` [Qemu-devel] [PULL] QOM CPUState patch queue 2012-12-19 Blue Swirl
2012-12-23 0:00 ` Andreas Färber
2012-12-28 20:05 ` Blue Swirl
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