From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlJpO-0007Mq-5a for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:36:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TlJpI-0004T9-Tw for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:36:54 -0500 Received: from cantor2.suse.de ([195.135.220.15]:60371 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlJpI-0004So-Hc for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:36:48 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 16991A5204 for ; Wed, 19 Dec 2012 14:36:48 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 19 Dec 2012 14:36:18 +0100 Message-Id: <1355924196-19288-3-git-send-email-afaerber@suse.de> In-Reply-To: <1355924196-19288-1-git-send-email-afaerber@suse.de> References: <1355924196-19288-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 02/20] alpha: Pass AlphaCPU array to Typhoon List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Also store it in TyphoonCchip. Signed-off-by: Andreas F=C3=A4rber Acked-by: Richard Henderson --- hw/alpha_dp264.c | 18 +++++++++--------- hw/alpha_sys.h | 2 +- hw/alpha_typhoon.c | 29 ++++++++++++++++------------- 3 Dateien ge=C3=A4ndert, 26 Zeilen hinzugef=C3=BCgt(+), 23 Zeilen entfer= nt(-) diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c index 76d8ae8..af24d1e 100644 --- a/hw/alpha_dp264.c +++ b/hw/alpha_dp264.c @@ -50,7 +50,7 @@ static void clipper_init(QEMUMachineInitArgs *args) const char *kernel_filename =3D args->kernel_filename; const char *kernel_cmdline =3D args->kernel_cmdline; const char *initrd_filename =3D args->initrd_filename; - CPUAlphaState *cpus[4]; + AlphaCPU *cpus[4]; PCIBus *pci_bus; ISABus *isa_bus; qemu_irq rtc_irq; @@ -62,12 +62,12 @@ static void clipper_init(QEMUMachineInitArgs *args) /* Create up to 4 cpus. */ memset(cpus, 0, sizeof(cpus)); for (i =3D 0; i < smp_cpus; ++i) { - cpus[i] =3D cpu_init(cpu_model ? cpu_model : "ev67"); + cpus[i] =3D cpu_alpha_init(cpu_model ? cpu_model : "ev67"); } =20 - cpus[0]->trap_arg0 =3D ram_size; - cpus[0]->trap_arg1 =3D 0; - cpus[0]->trap_arg2 =3D smp_cpus; + cpus[0]->env.trap_arg0 =3D ram_size; + cpus[0]->env.trap_arg1 =3D 0; + cpus[0]->env.trap_arg2 =3D smp_cpus; =20 /* Init the chipset. */ pci_bus =3D typhoon_init(ram_size, &isa_bus, &rtc_irq, cpus, @@ -119,9 +119,9 @@ static void clipper_init(QEMUMachineInitArgs *args) =20 /* Start all cpus at the PALcode RESET entry point. */ for (i =3D 0; i < smp_cpus; ++i) { - cpus[i]->pal_mode =3D 1; - cpus[i]->pc =3D palcode_entry; - cpus[i]->palbr =3D palcode_entry; + cpus[i]->env.pal_mode =3D 1; + cpus[i]->env.pc =3D palcode_entry; + cpus[i]->env.palbr =3D palcode_entry; } =20 /* Load a kernel. */ @@ -136,7 +136,7 @@ static void clipper_init(QEMUMachineInitArgs *args) exit(1); } =20 - cpus[0]->trap_arg1 =3D kernel_entry; + cpus[0]->env.trap_arg1 =3D kernel_entry; =20 param_offset =3D kernel_low - 0x6000; =20 diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h index 7604d09..69929ea 100644 --- a/hw/alpha_sys.h +++ b/hw/alpha_sys.h @@ -11,7 +11,7 @@ #include "irq.h" =20 =20 -PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[= 4], +PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4], pci_map_irq_fn); =20 /* alpha_pci.c. */ diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index 9b16d96..4cc810f 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -23,7 +23,7 @@ typedef struct TyphoonCchip { uint64_t drir; uint64_t dim[4]; uint32_t iic[4]; - CPUAlphaState *cpu[4]; + AlphaCPU *cpu[4]; } TyphoonCchip; =20 typedef struct TyphoonWindow { @@ -58,10 +58,11 @@ typedef struct TyphoonState { } TyphoonState; =20 /* Called when one of DRIR or DIM changes. */ -static void cpu_irq_change(CPUAlphaState *env, uint64_t req) +static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) { /* If there are any non-masked interrupts, tell the cpu. */ - if (env) { + if (cpu !=3D NULL) { + CPUAlphaState *env =3D &cpu->env; if (req) { cpu_interrupt(env, CPU_INTERRUPT_HARD); } else { @@ -353,8 +354,9 @@ static void cchip_write(void *opaque, hwaddr addr, if ((newval ^ oldval) & 0xff0) { int i; for (i =3D 0; i < 4; ++i) { - CPUAlphaState *env =3D s->cchip.cpu[i]; - if (env) { + AlphaCPU *cpu =3D s->cchip.cpu[i]; + if (cpu !=3D NULL) { + CPUAlphaState *env =3D &cpu->env; /* IPI can be either cleared or set by the write. *= / if (newval & (1 << (i + 8))) { cpu_interrupt(env, CPU_INTERRUPT_SMP); @@ -661,8 +663,8 @@ static void typhoon_set_timer_irq(void *opaque, int i= rq, int level) =20 /* Deliver the interrupt to each CPU, considering each CPU's IIC. *= / for (i =3D 0; i < 4; ++i) { - CPUAlphaState *env =3D s->cchip.cpu[i]; - if (env) { + AlphaCPU *cpu =3D s->cchip.cpu[i]; + if (cpu !=3D NULL) { uint32_t iic =3D s->cchip.iic[i]; =20 /* ??? The verbage in Section 10.2.2.10 isn't 100% clear. @@ -681,7 +683,7 @@ static void typhoon_set_timer_irq(void *opaque, int i= rq, int level) /* Set the ITI bit for this cpu. */ s->cchip.misc |=3D 1 << (i + 4); /* And signal the interrupt. */ - cpu_interrupt(env, CPU_INTERRUPT_TIMER); + cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER); } } } @@ -694,12 +696,12 @@ static void typhoon_alarm_timer(void *opaque) =20 /* Set the ITI bit for this cpu. */ s->cchip.misc |=3D 1 << (cpu + 4); - cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER); + cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER); } =20 PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, qemu_irq *p_rtc_irq, - CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq) + AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) { const uint64_t MB =3D 1024 * 1024; const uint64_t GB =3D 1024 * MB; @@ -719,9 +721,10 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **i= sa_bus, =20 /* Remember the CPUs so that we can deliver interrupts to them. */ for (i =3D 0; i < 4; i++) { - CPUAlphaState *env =3D cpus[i]; - s->cchip.cpu[i] =3D env; - if (env) { + AlphaCPU *cpu =3D cpus[i]; + s->cchip.cpu[i] =3D cpu; + if (cpu !=3D NULL) { + CPUAlphaState *env =3D &cpu->env; env->alarm_timer =3D qemu_new_timer_ns(rtc_clock, typhoon_alarm_timer, (void *)((uintptr_t)s += i)); --=20 1.7.10.4