From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlJpP-0007NE-1k for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:37:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TlJpK-0004Ta-0o for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:36:54 -0500 Received: from cantor2.suse.de ([195.135.220.15]:60376 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlJpJ-0004TS-KG for qemu-devel@nongnu.org; Wed, 19 Dec 2012 08:36:49 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 19 Dec 2012 14:36:20 +0100 Message-Id: <1355924196-19288-5-git-send-email-afaerber@suse.de> In-Reply-To: <1355924196-19288-1-git-send-email-afaerber@suse.de> References: <1355924196-19288-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 04/20] target-alpha: Turn CPU definitions into subclasses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson Make TYPE_ALPHA_CPU abstract and add types -alpha-cpu. Use type inheritence, and turn "2*" models into aliases. Move cpu_alpha_init() to cpu.c and split out CPU realization. Default to creating type "ev67-alpha-cpu" as before. Signed-off-by: Andreas F=C3=A4rber Acked-by: Richard Henderson --- target-alpha/cpu.c | 178 ++++++++++++++++++++++++++++++++++++++++= +++++- target-alpha/cpu.h | 2 + target-alpha/translate.c | 58 +-------------- 3 Dateien ge=C3=A4ndert, 180 Zeilen hinzugef=C3=BCgt(+), 58 Zeilen entfe= rnt(-) diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 11a19eb..a5a98d0 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -21,8 +21,175 @@ =20 #include "cpu.h" #include "qemu-common.h" +#include "error.h" =20 =20 +static void alpha_cpu_realize(Object *obj, Error **errp) +{ +#ifndef CONFIG_USER_ONLY + AlphaCPU *cpu =3D ALPHA_CPU(obj); + + qemu_init_vcpu(&cpu->env); +#endif +} + +/* Models */ + +#define TYPE(model) model "-" TYPE_ALPHA_CPU + +typedef struct AlphaCPUAlias { + const char *alias; + const char *typename; +} AlphaCPUAlias; + +static const AlphaCPUAlias alpha_cpu_aliases[] =3D { + { "21064", TYPE("ev4") }, + { "21164", TYPE("ev5") }, + { "21164a", TYPE("ev56") }, + { "21164pc", TYPE("pca56") }, + { "21264", TYPE("ev6") }, + { "21264a", TYPE("ev67") }, +}; + +static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc =3D NULL; + char *typename; + int i; + + if (cpu_model =3D=3D NULL) { + return NULL; + } + + oc =3D object_class_by_name(cpu_model); + if (oc !=3D NULL) { + return oc; + } + + for (i =3D 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { + if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) =3D=3D 0) { + oc =3D object_class_by_name(alpha_cpu_aliases[i].typename); + assert(oc !=3D NULL); + return oc; + } + } + + typename =3D g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + return oc; +} + +AlphaCPU *cpu_alpha_init(const char *cpu_model) +{ + AlphaCPU *cpu; + CPUAlphaState *env; + ObjectClass *cpu_class; + + cpu_class =3D alpha_cpu_class_by_name(cpu_model); + if (cpu_class =3D=3D NULL) { + /* Default to ev67; no reason not to emulate insns by default. = */ + cpu_class =3D object_class_by_name(TYPE("ev67")); + } + cpu =3D ALPHA_CPU(object_new(object_class_get_name(cpu_class))); + env =3D &cpu->env; + + env->cpu_model_str =3D cpu_model; + + alpha_cpu_realize(OBJECT(cpu), NULL); + return cpu; +} + +static void ev4_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->implver =3D IMPLVER_2106x; +} + +static const TypeInfo ev4_cpu_type_info =3D { + .name =3D TYPE("ev4"), + .parent =3D TYPE_ALPHA_CPU, + .instance_init =3D ev4_cpu_initfn, +}; + +static void ev5_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->implver =3D IMPLVER_21164; +} + +static const TypeInfo ev5_cpu_type_info =3D { + .name =3D TYPE("ev5"), + .parent =3D TYPE_ALPHA_CPU, + .instance_init =3D ev5_cpu_initfn, +}; + +static void ev56_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->amask |=3D AMASK_BWX; +} + +static const TypeInfo ev56_cpu_type_info =3D { + .name =3D TYPE("ev56"), + .parent =3D TYPE("ev5"), + .instance_init =3D ev56_cpu_initfn, +}; + +static void pca56_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->amask |=3D AMASK_MVI; +} + +static const TypeInfo pca56_cpu_type_info =3D { + .name =3D TYPE("pca56"), + .parent =3D TYPE("ev56"), + .instance_init =3D pca56_cpu_initfn, +}; + +static void ev6_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->implver =3D IMPLVER_21264; + env->amask =3D AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; +} + +static const TypeInfo ev6_cpu_type_info =3D { + .name =3D TYPE("ev6"), + .parent =3D TYPE_ALPHA_CPU, + .instance_init =3D ev6_cpu_initfn, +}; + +static void ev67_cpu_initfn(Object *obj) +{ + AlphaCPU *cpu =3D ALPHA_CPU(obj); + CPUAlphaState *env =3D &cpu->env; + + env->amask |=3D AMASK_CIX | AMASK_PREFETCH; +} + +static const TypeInfo ev67_cpu_type_info =3D { + .name =3D TYPE("ev67"), + .parent =3D TYPE("ev6"), + .instance_init =3D ev67_cpu_initfn, +}; + +static const TypeInfo ev68_cpu_type_info =3D { + .name =3D TYPE("ev68"), + .parent =3D TYPE("ev67"), +}; + static void alpha_cpu_initfn(Object *obj) { AlphaCPU *cpu =3D ALPHA_CPU(obj); @@ -31,6 +198,8 @@ static void alpha_cpu_initfn(Object *obj) cpu_exec_init(env); tlb_flush(env, 1); =20 + alpha_translate_init(); + #if defined(CONFIG_USER_ONLY) env->ps =3D PS_USER_MODE; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD @@ -46,13 +215,20 @@ static const TypeInfo alpha_cpu_type_info =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(AlphaCPU), .instance_init =3D alpha_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(AlphaCPUClass), }; =20 static void alpha_cpu_register_types(void) { type_register_static(&alpha_cpu_type_info); + type_register_static(&ev4_cpu_type_info); + type_register_static(&ev5_cpu_type_info); + type_register_static(&ev56_cpu_type_info); + type_register_static(&pca56_cpu_type_info); + type_register_static(&ev6_cpu_type_info); + type_register_static(&ev67_cpu_type_info); + type_register_static(&ev68_cpu_type_info); } =20 type_init(alpha_cpu_register_types) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index e1d7715..0d08458 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -425,6 +425,8 @@ enum { IR_ZERO =3D 31, }; =20 +void alpha_translate_init(void); + AlphaCPU *cpu_alpha_init(const char *cpu_model); =20 static inline CPUAlphaState *cpu_init(const char *cpu_model) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 6f41ef7..dc0c97c 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -90,7 +90,7 @@ static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; =20 #include "gen-icount.h" =20 -static void alpha_translate_init(void) +void alpha_translate_init(void) { int i; char *p; @@ -3493,62 +3493,6 @@ void gen_intermediate_code_pc (CPUAlphaState *env,= struct TranslationBlock *tb) gen_intermediate_code_internal(env, tb, 1); } =20 -struct cpu_def_t { - const char *name; - int implver, amask; -}; - -static const struct cpu_def_t cpu_defs[] =3D { - { "ev4", IMPLVER_2106x, 0 }, - { "ev5", IMPLVER_21164, 0 }, - { "ev56", IMPLVER_21164, AMASK_BWX }, - { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI }, - { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_= TRAP }, - { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX - | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, - { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX - | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, - { "21064", IMPLVER_2106x, 0 }, - { "21164", IMPLVER_21164, 0 }, - { "21164a", IMPLVER_21164, AMASK_BWX }, - { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI }, - { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_= TRAP }, - { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX - | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), } -}; - -AlphaCPU *cpu_alpha_init(const char *cpu_model) -{ - AlphaCPU *cpu; - CPUAlphaState *env; - int implver, amask, i, max; - - cpu =3D ALPHA_CPU(object_new(TYPE_ALPHA_CPU)); - env =3D &cpu->env; - - alpha_translate_init(); - - /* Default to ev67; no reason not to emulate insns by default. */ - implver =3D IMPLVER_21264; - amask =3D (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI - | AMASK_TRAP | AMASK_PREFETCH); - - max =3D ARRAY_SIZE(cpu_defs); - for (i =3D 0; i < max; i++) { - if (strcmp (cpu_model, cpu_defs[i].name) =3D=3D 0) { - implver =3D cpu_defs[i].implver; - amask =3D cpu_defs[i].amask; - break; - } - } - env->implver =3D implver; - env->amask =3D amask; - env->cpu_model_str =3D cpu_model; - - qemu_init_vcpu(env); - return cpu; -} - void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int = pc_pos) { env->pc =3D tcg_ctx.gen_opc_pc[pc_pos]; --=20 1.7.10.4