From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlMA5-0007rd-23 for qemu-devel@nongnu.org; Wed, 19 Dec 2012 11:06:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TlMA3-0001nW-Kp for qemu-devel@nongnu.org; Wed, 19 Dec 2012 11:06:24 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TlMA3-0001nM-Cx for qemu-devel@nongnu.org; Wed, 19 Dec 2012 11:06:23 -0500 Message-ID: <1355933177.3224.568.camel@bling.home> From: Alex Williamson Date: Wed, 19 Dec 2012 09:06:17 -0700 In-Reply-To: <1355906821-22928-1-git-send-email-xudong.hao@intel.com> References: <1355906821-22928-1-git-send-email-xudong.hao@intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] qemu-kvm/pci-assign: 64 bits bar emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Xudong Hao Cc: mtosatti@redhat.com, qemu-devel@nongnu.org, gleb@redhat.com, kvm@vger.kernel.org On Wed, 2012-12-19 at 16:47 +0800, Xudong Hao wrote: > Enable 64 bits bar emulation. > > v2 changes from v1: > - Change 0lx% to 0x%016 when print a 64 bit variable. > > Test pass with the current seabios which already support 64bit pci bars. > > Signed-off-by: Xudong Hao > --- > hw/kvm/pci-assign.c | 22 ++++++++++++++-------- > 1 files changed, 14 insertions(+), 8 deletions(-) > > diff --git a/hw/kvm/pci-assign.c b/hw/kvm/pci-assign.c > index 7a0998c..fb58ca9 100644 > --- a/hw/kvm/pci-assign.c > +++ b/hw/kvm/pci-assign.c > @@ -46,6 +46,7 @@ > #define IORESOURCE_IRQ 0x00000400 > #define IORESOURCE_DMA 0x00000800 > #define IORESOURCE_PREFETCH 0x00002000 /* No side effects */ > +#define IORESOURCE_MEM_64 0x00100000 > > //#define DEVICE_ASSIGNMENT_DEBUG > > @@ -442,9 +443,13 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, > > /* handle memory io regions */ > if (cur_region->type & IORESOURCE_MEM) { > - int t = cur_region->type & IORESOURCE_PREFETCH > - ? PCI_BASE_ADDRESS_MEM_PREFETCH > - : PCI_BASE_ADDRESS_SPACE_MEMORY; > + int t = PCI_BASE_ADDRESS_SPACE_MEMORY; > + if (cur_region->type & IORESOURCE_PREFETCH) { > + t |= PCI_BASE_ADDRESS_MEM_PREFETCH; > + } > + if (cur_region->type & IORESOURCE_MEM_64) { > + t |= PCI_BASE_ADDRESS_MEM_TYPE_64; > + } > > /* map physical memory */ > pci_dev->v_addrs[i].u.r_virtbase = mmap(NULL, cur_region->size, > @@ -468,10 +473,10 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, > (cur_region->base_addr & 0xFFF); > > if (cur_region->size & 0xFFF) { > - error_report("PCI region %d at address 0x%" PRIx64 " has " > - "size 0x%" PRIx64 ", which is not a multiple of " > - "4K. You might experience some performance hit " > - "due to that.", > + error_report("PCI region %d at address 0x%016" PRIx64 " has " > + "size 0x%016" PRIx64 ", which is not a multiple " > + "of 4K. You might experience some performance " > + "hit due to that.", nit, these changes to %016 don't make sense. If the size is not a multiple of 4k, then it's less than 4k, so adding leading zeros is just a waste. Also, are BARs that small likely to be 64bit? Seems like not, so more unnecessary zeros. Thanks, Alex > i, cur_region->base_addr, cur_region->size); > memory_region_init_io(&pci_dev->v_addrs[i].real_iomem, > &slow_bar_ops, &pci_dev->v_addrs[i], > @@ -632,7 +637,8 @@ again: > rp->valid = 0; > rp->resource_fd = -1; > size = end - start + 1; > - flags &= IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH; > + flags &= IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH > + | IORESOURCE_MEM_64; > if (size == 0 || (flags & ~IORESOURCE_PREFETCH) == 0) { > continue; > }