[Qemu-devel] [PATCH 02/15] openpic: lower interrupt when reading the MSI register

[Scott Wood <scottwood@freescale.com>]

This will stop things from breaking once it's properly treated as a
level-triggered interrupt.  Note that it's the MPIC's MSI cascade
interrupts that are level-triggered; the individual MSIs are
edge-triggered.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 hw/openpic.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/openpic.c b/hw/openpic.c
index 72a5bc9..02f793b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -801,6 +801,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
         r = opp->msi[srs].msir;
         /* Clear on read */
         opp->msi[srs].msir = 0;
+        openpic_set_irq(opp, opp->irq_msi + srs, 0);
         break;
     case 0x120: /* MSISR */
         for (i = 0; i < MAX_MSI; i++) {
-- 
1.7.9.5