From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TmEdL-0008UX-LL for qemu-devel@nongnu.org; Fri, 21 Dec 2012 21:16:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TmEdH-0006Bw-7d for qemu-devel@nongnu.org; Fri, 21 Dec 2012 21:16:15 -0500 From: Scott Wood Date: Fri, 21 Dec 2012 20:15:39 -0600 Message-ID: <1356142552-13453-3-git-send-email-scottwood@freescale.com> In-Reply-To: <1356142552-13453-1-git-send-email-scottwood@freescale.com> References: <1356142552-13453-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 02/15] openpic: lower interrupt when reading the MSI register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Scott Wood , qemu-ppc@nongnu.org, qemu-devel@nongnu.org This will stop things from breaking once it's properly treated as a level-triggered interrupt. Note that it's the MPIC's MSI cascade interrupts that are level-triggered; the individual MSIs are edge-triggered. Signed-off-by: Scott Wood --- hw/openpic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/openpic.c b/hw/openpic.c index 72a5bc9..02f793b 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -801,6 +801,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) r = opp->msi[srs].msir; /* Clear on read */ opp->msi[srs].msir = 0; + openpic_set_irq(opp, opp->irq_msi + srs, 0); break; case 0x120: /* MSISR */ for (i = 0; i < MAX_MSI; i++) { -- 1.7.9.5