From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tqr9m-00020d-8N for qemu-devel@nongnu.org; Thu, 03 Jan 2013 15:12:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tqr9j-0004t9-Sr for qemu-devel@nongnu.org; Thu, 03 Jan 2013 15:12:50 -0500 Date: Thu, 3 Jan 2013 14:12:35 -0600 From: Scott Wood References: <1356142552-13453-1-git-send-email-scottwood@freescale.com> <1356142552-13453-4-git-send-email-scottwood@freescale.com> <9F4AB582-B28A-47D6-AC54-FE0C0B9A062D@suse.de> In-Reply-To: <9F4AB582-B28A-47D6-AC54-FE0C0B9A062D@suse.de> (from agraf@suse.de on Thu Jan 3 11:51:56 2013) Message-ID: <1357243955.22404.6@snotra> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; delsp=Yes; format=Flowed Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 03/15] openpic: fix sense and priority bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 01/03/2013 11:51:56 AM, Alexander Graf wrote: >=20 > On 22.12.2012, at 03:15, Scott Wood wrote: >=20 > > Previously, the sense and priority bits were masked off when writing > > to IVPR, and all interrupts were treated as edge-triggered (despite > > the existence of code for handling level-triggered interrupts). > > > > Polarity is implemented only as storage. We don't simulate the > > bad effects that you'd get on real hardware if you set this =20 > incorrectly, > > but at least the guest sees the right thing when it reads back the =20 > register. > > > > Sense now controls level/edge on FSL external interrupts (and all > > interrupts on non-FSL MPIC). FSL internal interrupts do not have a =20 > sense > > bit (reads as zero), but are level. FSL timers and IPIs do not have > > sense or polarity bits (read as zero), and are edge-triggered. To > > accommodate FSL internal interrupts, QEMU's internal notion of =20 > whether an > > interrupt is level-triggered is separated from the IVPR bit. > > > > Signed-off-by: Scott Wood > > --- > > hw/openpic.c | 61 =20 > ++++++++++++++++++++++++++++++++++++++++++++++++++++------ > > 1 file changed, 55 insertions(+), 6 deletions(-) > > > > diff --git a/hw/openpic.c b/hw/openpic.c > > index 02f793b..34449a7 100644 > > --- a/hw/openpic.c > > +++ b/hw/openpic.c > > @@ -189,6 +189,9 @@ typedef struct IRQ_src_t { > > uint32_t ide; /* IRQ destination register */ > > int last_cpu; > > int pending; /* TRUE if IRQ is pending */ > > + bool level; /* level-triggered */ > > + bool fslint; /* FSL internal interrupt -- level only */ > > + bool fslspecial; /* FSL timer/IPI interrupt, edge, no polarity =20 > */ >=20 > This really looks more like an "irqtype" enum, no? >=20 > enum irqtype { > IRQ_TYPE_NORMAL =3D 0, > IRQ_TYPE_FSLINT, > IRQ_TYPE_FSLSPECIAL, > } OK. At one point they could both be set, before I looked more closely =20 at how the special interrupts are defined in hardware. -Scott=