From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TrCMM-0005Vg-O8 for qemu-devel@nongnu.org; Fri, 04 Jan 2013 13:51:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TrCMI-0004D2-SS for qemu-devel@nongnu.org; Fri, 04 Jan 2013 13:51:14 -0500 Date: Fri, 4 Jan 2013 12:50:53 -0600 From: Scott Wood In-Reply-To: <1357295099-23971-1-git-send-email-agraf@suse.de> (from agraf@suse.de on Fri Jan 4 04:24:59 2013) Message-ID: <1357325453.666.10@snotra> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; delsp=Yes; format=Flowed Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] PPC: Bring EPR support closer to reality List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 01/04/2013 04:24:59 AM, Alexander Graf wrote: > We already used to support the external proxy facility of FSL MPICs, > but only implemented it halfway correctly. >=20 > This patch adds support for >=20 > * dynamic enablement of the EPR facility > * interrupt acknowledgement only when the interrupt is delivered >=20 > This way the implementation now is closer to real hardware. >=20 > Signed-off-by: Alexander Graf > --- > hw/openpic.c | 20 ++++++++++++++++++++ > target-ppc/Makefile.objs | 1 - > target-ppc/cpu.h | 2 ++ > target-ppc/excp_helper.c | 4 ++++ > target-ppc/helper.h | 1 - > target-ppc/mpic_helper.c | 35 =20 > ----------------------------------- > target-ppc/translate_init.c | 7 +------ > 7 files changed, 27 insertions(+), 43 deletions(-) > delete mode 100644 target-ppc/mpic_helper.c >=20 > diff --git a/hw/openpic.c b/hw/openpic.c > index e773d68..6447a47 100644 > --- a/hw/openpic.c > +++ b/hw/openpic.c > @@ -131,6 +131,9 @@ static const int debug_openpic =3D 0; > #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ >=20 > #define GCR_RESET 0x80000000 > +#define GCR_MODE_PASS 0x00000000 > +#define GCR_MODE_MIXED 0x20000000 > +#define GCR_MODE_PROXY 0x60000000 >=20 > #define TBCR_CI 0x80000000 /* count inhibit */ > #define TCCR_TOG 0x80000000 /* toggles when decrement to =20 > zero */ > @@ -233,6 +236,7 @@ typedef struct OpenPICState { > uint32_t ivpr_reset; > uint32_t idr_reset; > uint32_t brr1; > + uint32_t mpic_mode_mask; >=20 > /* Sub-regions */ > MemoryRegion sub_io_mem[5]; > @@ -667,6 +671,20 @@ static void openpic_gbl_write(void *opaque, =20 > hwaddr addr, uint64_t val, > case 0x1020: /* GCR */ > if (val & GCR_RESET) { > openpic_reset(&opp->busdev.qdev); > + } else if (opp->mpic_mode_mask) { > + CPUArchState *env; > + int mpic_proxy =3D 0; > + > + opp->gcr &=3D ~opp->mpic_mode_mask; > + opp->gcr |=3D val & opp->mpic_mode_mask; > + > + /* Set external proxy mode */ > + if ((val & opp->mpic_mode_mask) =3D=3D GCR_MODE_PROXY) { > + mpic_proxy =3D 1; > + } > + for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu= ) { > + env->mpic_proxy =3D mpic_proxy; > + } > } > break; > case 0x1080: /* VIR */ > @@ -1407,6 +1425,8 @@ static int openpic_init(SysBusDevice *dev) > opp->irq_tim0 =3D FSL_MPIC_20_TMR_IRQ; > opp->irq_msi =3D FSL_MPIC_20_MSI_IRQ; > opp->brr1 =3D FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN; > + opp->mpic_mode_mask =3D GCR_MODE_PROXY; > + Technically this should only be available starting with v4.0, but I =20 guess that can wait until we have more general support for a newer MPIC =20 model. Should at least have a comment, though. > msi_supported =3D true; > list =3D list_be; >=20 > diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs > index 237a0ed..6c11ef8 100644 > --- a/target-ppc/Makefile.objs > +++ b/target-ppc/Makefile.objs > @@ -9,4 +9,3 @@ obj-y +=3D mmu_helper.o > obj-y +=3D timebase_helper.o > obj-y +=3D misc_helper.o > obj-y +=3D mem_helper.o > -obj-y +=3D mpic_helper.o > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index e88ebe0..0db06d6 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1068,6 +1068,8 @@ struct CPUPPCState { > target_ulong ivpr_mask; > target_ulong hreset_vector; > hwaddr mpic_cpu_base; > + /* true when the external proxy facility mode is enabled */ > + int mpic_proxy; > #endif bool? > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > index 41037a7..2b80164 100644 > --- a/target-ppc/excp_helper.c > +++ b/target-ppc/excp_helper.c > @@ -178,6 +178,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, =20 > int excp_model, int excp) > if (lpes0 =3D=3D 1) { > new_msr |=3D (target_ulong)MSR_HVB; > } > + if (env->mpic_proxy) { > + /* IACK the IRQ on delivery */ > + env->spr[SPR_BOOKE_EPR] =3D ldl_phys(env->mpic_cpu_base + =20 > 0xA0); > + } Can we avoid the opencoded 0xA0? QEMU has too many open-coded magic =20 numbers as is. I don't see where mpic_cpu_base is used other than for EPR; maybe just =20 change it to mpic_iack? Or are there plans to do other things with it? -Scott=