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Date: Mon, 7 Jan 2013 11:42:22 -0600
From: Scott Wood <scottwood@freescale.com>
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	agraf@suse.de on Fri Jan  4 17:36:42 2013)
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Subject: Re: [Qemu-devel] [PATCH] PPC: Bring EPR support closer to reality
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To: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On 01/04/2013 05:36:42 PM, Alexander Graf wrote:
> @@ -667,6 +671,20 @@ static void openpic_gbl_write(void *opaque, =20
> hwaddr addr, uint64_t val,
>      case 0x1020: /* GCR */
>          if (val & GCR_RESET) {
>              openpic_reset(&opp->busdev.qdev);
> +        } else if (opp->mpic_mode_mask) {
> +            CPUArchState *env;
> +            int mpic_proxy =3D 0;
> +
> +            opp->gcr &=3D ~opp->mpic_mode_mask;
> +            opp->gcr |=3D val & opp->mpic_mode_mask;
> +
> +            /* Set external proxy mode */
> +            if ((val & opp->mpic_mode_mask) =3D=3D GCR_MODE_PROXY) {
> +                mpic_proxy =3D 1;
> +            }
> +            for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu=
) {
> +                env->mpic_proxy =3D mpic_proxy;
> +            }
>          }
>          break;
>      case 0x1080: /* VIR */

Why is "if (opp->mpic_mode_mask)" needed?  The code should already be a
no-op if mpic_mode_mask is zero.

Can get rid of the "else" by having the reset code do a "break".

> @@ -1407,6 +1425,9 @@ static int openpic_init(SysBusDevice *dev)
>          opp->irq_tim0 =3D FSL_MPIC_20_TMR_IRQ;
>          opp->irq_msi =3D FSL_MPIC_20_MSI_IRQ;
>          opp->brr1 =3D FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
> +        /* XXX really only available as of MPIC 4.0 */
> +        opp->mpic_mode_mask =3D GCR_MODE_PROXY;
> +

Shouldn't mpic_mode_mask be set to GCR_MODE_MIXED for Raven?

-Scott=