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Date: Mon, 7 Jan 2013 13:04:28 -0600
From: Scott Wood <scottwood@freescale.com>
In-Reply-To: <D88655F4-2A4A-4A49-8D20-C456A56D6A8C@suse.de> (from
	agraf@suse.de on Mon Jan  7 11:50:02 2013)
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Subject: Re: [Qemu-devel] [PATCH] PPC: Bring EPR support closer to reality
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To: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On 01/07/2013 11:50:02 AM, Alexander Graf wrote:
> >> @@ -1407,6 +1425,9 @@ static int openpic_init(SysBusDevice *dev)
> >>         opp->irq_tim0 =3D FSL_MPIC_20_TMR_IRQ;
> >>         opp->irq_msi =3D FSL_MPIC_20_MSI_IRQ;
> >>         opp->brr1 =3D FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
> >> +        /* XXX really only available as of MPIC 4.0 */
> >> +        opp->mpic_mode_mask =3D GCR_MODE_PROXY;
> >> +
> >
> > Shouldn't mpic_mode_mask be set to GCR_MODE_MIXED for Raven?
>=20
> Does Raven support the MIXED bit?

Yes.  It's part of the base openpic spec (though it calls the bit "8259 =20
pass through disable").

> Do you have a pointer to the spec?

http://www.slac.stanford.edu/grp/cd/soft/vxworks/doc/cpu/pci/ppc/mcp750/mcp=
750pg.pdf

-Scott=