[Qemu-devel] [PATCH ppc-next 0/3] openpic: improve GCR register handling

[Qemu-devel] [PATCH ppc-next 0/3] openpic: improve GCR register handling

[Alexander Graf]

This patch set improves handling of the GCR register to accomodate
Scott's comments during patch review.

Alexander Graf (3):
  openpic: move gcr write into a function
  openpic: unify gcr mode mask updates
  openpic: set mixed mode as supported

 hw/openpic.c |   41 ++++++++++++++++++++++++-----------------
 1 files changed, 24 insertions(+), 17 deletions(-)

[Qemu-devel] [PATCH ppc-next 1/3] openpic: move gcr write into a function

[Alexander Graf]

The GCR register contains too much functionality to be covered inside
of the register switch statement. Move it out into a separate function.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   39 ++++++++++++++++++++++-----------------
 1 files changed, 22 insertions(+), 17 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 3b20a39..344f97f 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -641,6 +641,27 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
             opp->src[n_IRQ].ivpr);
 }
 
+static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
+{
+    if (val & GCR_RESET) {
+        openpic_reset(&opp->busdev.qdev);
+    } else if (opp->mpic_mode_mask) {
+        CPUArchState *env;
+        int mpic_proxy = 0;
+
+        opp->gcr &= ~opp->mpic_mode_mask;
+        opp->gcr |= val & opp->mpic_mode_mask;
+
+        /* Set external proxy mode */
+        if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
+            mpic_proxy = 1;
+        }
+        for (env = first_cpu; env != NULL; env = env->next_cpu) {
+            env->mpic_proxy = mpic_proxy;
+        }
+    }
+}
+
 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
                               unsigned len)
 {
@@ -669,23 +690,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
     case 0x1000: /* FRR */
         break;
     case 0x1020: /* GCR */
-        if (val & GCR_RESET) {
-            openpic_reset(&opp->busdev.qdev);
-        } else if (opp->mpic_mode_mask) {
-            CPUArchState *env;
-            int mpic_proxy = 0;
-
-            opp->gcr &= ~opp->mpic_mode_mask;
-            opp->gcr |= val & opp->mpic_mode_mask;
-
-            /* Set external proxy mode */
-            if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
-                mpic_proxy = 1;
-            }
-            for (env = first_cpu; env != NULL; env = env->next_cpu) {
-                env->mpic_proxy = mpic_proxy;
-            }
-        }
+        openpic_gcr_write(opp, val);
         break;
     case 0x1080: /* VIR */
         break;
-- 
1.6.0.2

[Qemu-devel] [PATCH ppc-next 2/3] openpic: unify gcr mode mask updates

[Alexander Graf]

The mode mask already masks out bits we don't care about, so the
actual handling code can stay intact regardless.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   25 +++++++++++++------------
 1 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 344f97f..713322b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -643,22 +643,23 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
 
 static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
 {
+    CPUArchState *env;
+    int mpic_proxy = 0;
+
     if (val & GCR_RESET) {
         openpic_reset(&opp->busdev.qdev);
-    } else if (opp->mpic_mode_mask) {
-        CPUArchState *env;
-        int mpic_proxy = 0;
+        return;
+    }
 
-        opp->gcr &= ~opp->mpic_mode_mask;
-        opp->gcr |= val & opp->mpic_mode_mask;
+    opp->gcr &= ~opp->mpic_mode_mask;
+    opp->gcr |= val & opp->mpic_mode_mask;
 
-        /* Set external proxy mode */
-        if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
-            mpic_proxy = 1;
-        }
-        for (env = first_cpu; env != NULL; env = env->next_cpu) {
-            env->mpic_proxy = mpic_proxy;
-        }
+    /* Set external proxy mode */
+    if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
+        mpic_proxy = 1;
+    }
+    for (env = first_cpu; env != NULL; env = env->next_cpu) {
+        env->mpic_proxy = mpic_proxy;
     }
 }
 
-- 
1.6.0.2

[Qemu-devel] [PATCH ppc-next 3/3] openpic: set mixed mode as supported

[Alexander Graf]

The Raven MPIC implementation supports the "Mixed" mode to work with
an i8259. While we don't implement mixed mode, we should mark it as
a supported mode in the mode bitmap.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 713322b..aeee479 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1467,6 +1467,7 @@ static int openpic_init(SysBusDevice *dev)
         opp->irq_ipi0 = RAVEN_IPI_IRQ;
         opp->irq_tim0 = RAVEN_TMR_IRQ;
         opp->brr1 = -1;
+        opp->mpic_mode_mask = GCR_MODE_MIXED;
         list = list_le;
         /* Don't map MSI region */
         list[2].map = false;
-- 
1.6.0.2