From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsIGX-0004Zc-Mo for qemu-devel@nongnu.org; Mon, 07 Jan 2013 14:21:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TsIGV-0000s6-O7 for qemu-devel@nongnu.org; Mon, 07 Jan 2013 14:21:45 -0500 From: Alexander Graf Date: Mon, 7 Jan 2013 20:21:37 +0100 Message-Id: <1357586499-11463-2-git-send-email-agraf@suse.de> In-Reply-To: <1357586499-11463-1-git-send-email-agraf@suse.de> References: <1357586499-11463-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH ppc-next 1/3] openpic: move gcr write into a function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Scott Wood , qemu-ppc@nongnu.org The GCR register contains too much functionality to be covered inside of the register switch statement. Move it out into a separate function. Signed-off-by: Alexander Graf --- hw/openpic.c | 39 ++++++++++++++++++++++----------------- 1 files changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 3b20a39..344f97f 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -641,6 +641,27 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) opp->src[n_IRQ].ivpr); } +static void openpic_gcr_write(OpenPICState *opp, uint64_t val) +{ + if (val & GCR_RESET) { + openpic_reset(&opp->busdev.qdev); + } else if (opp->mpic_mode_mask) { + CPUArchState *env; + int mpic_proxy = 0; + + opp->gcr &= ~opp->mpic_mode_mask; + opp->gcr |= val & opp->mpic_mode_mask; + + /* Set external proxy mode */ + if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { + mpic_proxy = 1; + } + for (env = first_cpu; env != NULL; env = env->next_cpu) { + env->mpic_proxy = mpic_proxy; + } + } +} + static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -669,23 +690,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1000: /* FRR */ break; case 0x1020: /* GCR */ - if (val & GCR_RESET) { - openpic_reset(&opp->busdev.qdev); - } else if (opp->mpic_mode_mask) { - CPUArchState *env; - int mpic_proxy = 0; - - opp->gcr &= ~opp->mpic_mode_mask; - opp->gcr |= val & opp->mpic_mode_mask; - - /* Set external proxy mode */ - if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { - mpic_proxy = 1; - } - for (env = first_cpu; env != NULL; env = env->next_cpu) { - env->mpic_proxy = mpic_proxy; - } - } + openpic_gcr_write(opp, val); break; case 0x1080: /* VIR */ break; -- 1.6.0.2