From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsgEI-0000R2-D9 for qemu-devel@nongnu.org; Tue, 08 Jan 2013 15:57:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TsgEH-0005At-BZ for qemu-devel@nongnu.org; Tue, 08 Jan 2013 15:57:02 -0500 Received: from cantor2.suse.de ([195.135.220.15]:45649 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TsgEG-0005Ak-Tx for qemu-devel@nongnu.org; Tue, 08 Jan 2013 15:57:01 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 8 Jan 2013 21:56:33 +0100 Message-Id: <1357678594-427-17-git-send-email-afaerber@suse.de> In-Reply-To: <1357678594-427-1-git-send-email-afaerber@suse.de> References: <1357678594-427-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 16/17] target-i386: Sanitize AMD's ext2_features at realize time List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Igor Mammedov , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Igor Mammedov When CPU properties are implemented, ext2_features may change between object_new(CPU) and cpu_realize_fn(). Sanitizing ext2_features for AMD based CPU at realize() time will keep current behavior after CPU features are converted to properties. Signed-off-by: Igor Mammedov Reviewed-by: Eduardo Habkost Signed-off-by: Andreas F=C3=A4rber --- target-i386/cpu.c | 21 +++++++++++---------- 1 Datei ge=C3=A4ndert, 11 Zeilen hinzugef=C3=BCgt(+), 10 Zeilen entfernt= (-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index a776e11..b40cc37 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1561,16 +1561,6 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_= model) object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000, "tsc-frequency", &error); =20 - /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits o= n - * CPUID[1].EDX. - */ - if (env->cpuid_vendor1 =3D=3D CPUID_VENDOR_AMD_1 && - env->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 && - env->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) { - env->cpuid_ext2_features &=3D ~CPUID_EXT2_AMD_ALIASES; - env->cpuid_ext2_features |=3D (def->features & CPUID_EXT2_AMD_AL= IASES); - } - object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &err= or); if (error) { fprintf(stderr, "%s\n", error_get_pretty(error)); @@ -2091,6 +2081,17 @@ void x86_cpu_realize(Object *obj, Error **errp) env->cpuid_level =3D 7; } =20 + /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits o= n + * CPUID[1].EDX. + */ + if (env->cpuid_vendor1 =3D=3D CPUID_VENDOR_AMD_1 && + env->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 && + env->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) { + env->cpuid_ext2_features &=3D ~CPUID_EXT2_AMD_ALIASES; + env->cpuid_ext2_features |=3D (env->cpuid_features + & CPUID_EXT2_AMD_ALIASES); + } + if (!kvm_enabled()) { env->cpuid_features &=3D TCG_FEATURES; env->cpuid_ext_features &=3D TCG_EXT_FEATURES; --=20 1.7.10.4