From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvBIq-0004ww-3T for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TvBIo-0004Gl-Oc for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:04 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39328 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvBIo-0004GZ-Dm for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:02 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 15 Jan 2013 19:31:48 +0100 Message-Id: <1358274710-19588-2-git-send-email-afaerber@suse.de> In-Reply-To: <1358274710-19588-1-git-send-email-afaerber@suse.de> References: <1358274710-19588-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 1/3] hw/dma.c: Fix conversion of ioport_register* to MemoryRegion List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Julien Grall , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Julien Grall The commit 582299336879504353e60c7937fbc70fea93f3da introduced a 1-shift = for some offset in DMA emulation. Before the previous commit, which converted ioport_register_* to MemoryRegion, the DMA controller registered 8 ioports with the following formula: base + ((8 + i) << d->shift) where 0 <=3D i < 8 When an IO occured within a Memory Region, DMA callback receives an offset relative to the start address. Here the start address is: base + (8 << d->shift). The offset should be: (i << d->shift). After the shift is reverted, the offsets are 0..7 not 1..8. Fixes LP#1089996. Reported-by: Andreas Gustafsson Signed-off-by: Julien Grall Signed-off-by: Andreas F=C3=A4rber --- hw/dma.c | 22 +++++++++++----------- 1 Datei ge=C3=A4ndert, 11 Zeilen hinzugef=C3=BCgt(+), 11 Zeilen entfernt= (-) diff --git a/hw/dma.c b/hw/dma.c index 0634baa..5bdf435 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -201,7 +201,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, =20 iport =3D (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x01: /* command */ + case 0x00: /* command */ if ((data !=3D 0) && (data & CMD_NOT_SUPPORTED)) { dolog("command %"PRIx64" not supported\n", data); return; @@ -209,7 +209,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, d->command =3D data; break; =20 - case 0x02: + case 0x01: ichan =3D data & 3; if (data & 4) { d->status |=3D 1 << (ichan + 4); @@ -221,7 +221,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, DMA_run(); break; =20 - case 0x03: /* single mask */ + case 0x02: /* single mask */ if (data & 4) d->mask |=3D 1 << (data & 3); else @@ -229,7 +229,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, DMA_run(); break; =20 - case 0x04: /* mode */ + case 0x03: /* mode */ { ichan =3D data & 3; #ifdef DEBUG_DMA @@ -248,23 +248,23 @@ static void write_cont(void *opaque, hwaddr nport, = uint64_t data, break; } =20 - case 0x05: /* clear flip flop */ + case 0x04: /* clear flip flop */ d->flip_flop =3D 0; break; =20 - case 0x06: /* reset */ + case 0x05: /* reset */ d->flip_flop =3D 0; d->mask =3D ~0; d->status =3D 0; d->command =3D 0; break; =20 - case 0x07: /* clear mask for all channels */ + case 0x06: /* clear mask for all channels */ d->mask =3D 0; DMA_run(); break; =20 - case 0x08: /* write mask for all channels */ + case 0x07: /* write mask for all channels */ d->mask =3D data; DMA_run(); break; @@ -289,11 +289,11 @@ static uint64_t read_cont(void *opaque, hwaddr npor= t, unsigned size) =20 iport =3D (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x08: /* status */ + case 0x00: /* status */ val =3D d->status; d->status &=3D 0xf0; break; - case 0x0f: /* mask */ + case 0x01: /* mask */ val =3D d->mask; break; default: @@ -468,7 +468,7 @@ void DMA_schedule(int nchan) static void dma_reset(void *opaque) { struct dma_cont *d =3D opaque; - write_cont(d, (0x06 << d->dshift), 0, 1); + write_cont(d, (0x05 << d->dshift), 0, 1); } =20 static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int = dma_len) --=20 1.7.10.4