From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvBIp-0004wv-Q8 for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TvBIo-0004Gd-8i for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:03 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39336 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvBIn-0004Fw-Vi for qemu-devel@nongnu.org; Tue, 15 Jan 2013 13:32:02 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 15 Jan 2013 19:31:50 +0100 Message-Id: <1358274710-19588-4-git-send-email-afaerber@suse.de> In-Reply-To: <1358274710-19588-1-git-send-email-afaerber@suse.de> References: <1358274710-19588-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 3/3] acpi_piix4: Do not use old_portio-style callbacks List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Herv=C3=A9 Poussineau Signed-off-by: Herv=C3=A9 Poussineau [AF: Used HWADDR_PRIx for hwaddr PIIX4_DPRINTF()] Signed-off-by: Andreas F=C3=A4rber --- hw/acpi_piix4.c | 92 +++++++++++++++++++++++++------------------------= ------ 1 Datei ge=C3=A4ndert, 41 Zeilen hinzugef=C3=BCgt(+), 51 Zeilen entfernt= (-) diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 2f84b4e..0d33849 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -531,68 +531,58 @@ static const MemoryRegionOps piix4_gpe_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static uint32_t pci_up_read(void *opaque, uint32_t addr) +static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) { PIIX4PMState *s =3D opaque; - uint32_t val; - - /* Manufacture an "up" value to cause a device check on any hotplug - * slot with a device. Extra device checks are harmless. */ - val =3D s->pci0_slot_device_present & s->pci0_hotplug_enable; - - PIIX4_DPRINTF("pci_up_read %x\n", val); - return val; -} - -static uint32_t pci_down_read(void *opaque, uint32_t addr) -{ - PIIX4PMState *s =3D opaque; - uint32_t val =3D s->pci0_status.down; + uint32_t val =3D 0; + + switch (addr) { + case PCI_UP_BASE - PCI_HOTPLUG_ADDR: + /* Manufacture an "up" value to cause a device check on any hotp= lug + * slot with a device. Extra device checks are harmless. */ + val =3D s->pci0_slot_device_present & s->pci0_hotplug_enable; + PIIX4_DPRINTF("pci_up_read %x\n", val); + break; + case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: + val =3D s->pci0_status.down; + PIIX4_DPRINTF("pci_down_read %x\n", val); + break; + case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: + /* No feature defined yet */ + PIIX4_DPRINTF("pci_features_read %x\n", val); + break; + case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: + val =3D s->pci0_hotplug_enable; + break; + default: + break; + } =20 - PIIX4_DPRINTF("pci_down_read %x\n", val); return val; } =20 -static uint32_t pci_features_read(void *opaque, uint32_t addr) +static void pci_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) { - /* No feature defined yet */ - PIIX4_DPRINTF("pci_features_read %x\n", 0); - return 0; -} - -static void pciej_write(void *opaque, uint32_t addr, uint32_t val) -{ - acpi_piix_eject_slot(opaque, val); - - PIIX4_DPRINTF("pciej write %x <=3D=3D %d\n", addr, val); -} - -static uint32_t pcirmv_read(void *opaque, uint32_t addr) -{ - PIIX4PMState *s =3D opaque; - - return s->pci0_hotplug_enable; + switch (addr) { + case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: + acpi_piix_eject_slot(opaque, (uint32_t)data); + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <=3D=3D % " PRIu64 "= \n", + addr, data); + break; + default: + break; + } } =20 static const MemoryRegionOps piix4_pci_ops =3D { - .old_portio =3D (MemoryRegionPortio[]) { - { - .offset =3D PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len =3D 4, .s= ize =3D 4, - .read =3D pci_up_read, - },{ - .offset =3D PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len =3D 4, .s= ize =3D 4, - .read =3D pci_down_read, - },{ - .offset =3D PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len =3D 4, .s= ize =3D 4, - .read =3D pci_features_read, - .write =3D pciej_write, - },{ - .offset =3D PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len =3D 4, .s= ize =3D 4, - .read =3D pcirmv_read, - }, - PORTIO_END_OF_LIST() - }, + .read =3D pci_read, + .write =3D pci_write, .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }; =20 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, --=20 1.7.10.4