[Qemu-devel] [PATCH] hw/tpci200: Fix compiler warning (redefined symbol with MinGW)

[Stefan Weil <sw@weilnetz.de>]

STATUS_TIMEOUT is defined in winnt.h:

  CC    hw/tpci200.o
hw/tpci200.c:34:0:
 warning: "STATUS_TIMEOUT" redefined [enabled by default]
/usr/lib/gcc/x86_64-w64-mingw32/4.6/../../../../x86_64-w64-mingw32/include/winnt.h:1036:0:
 note: this is the location of the previous definition

Fix the compiler warning by adding a prefix.
The same prefix is also added to STATUS_INT and STATUS_ERR_ANY to
preserve uniformity of all three symbols.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
---
 hw/tpci200.c |   24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/tpci200.c b/hw/tpci200.c
index e082bca..c2a63ee 100644
--- a/hw/tpci200.c
+++ b/hw/tpci200.c
@@ -30,9 +30,9 @@
 #define IP_ID_SPACE_ADDR_MASK  0x3F
 #define IP_INT_SPACE_ADDR_MASK 0x3F
 
-#define STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
-#define STATUS_TIMEOUT(IP)    BIT((IP) + 12)
-#define STATUS_ERR_ANY        0xF00
+#define TPCI200_STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
+#define TPCI200_STATUS_TIMEOUT(IP)    BIT((IP) + 12)
+#define TPCI200_STATUS_ERR_ANY        0xF00
 
 #define CTRL_CLKRATE          BIT(0)
 #define CTRL_RECOVER          BIT(1)
@@ -119,9 +119,9 @@ static void tpci200_set_irq(void *opaque, int intno, int level)
 
     /* Update the interrupt status in the IP STATUS register */
     if (level) {
-        dev->status |=  STATUS_INT(ip_n, intno);
+        dev->status |=  TPCI200_STATUS_INT(ip_n, intno);
     } else {
-        dev->status &= ~STATUS_INT(ip_n, intno);
+        dev->status &= ~TPCI200_STATUS_INT(ip_n, intno);
     }
 
     /* Return if there are no changes */
@@ -147,7 +147,7 @@ static void tpci200_set_irq(void *opaque, int intno, int level)
         for (i = 0; i < N_MODULES; i++) {
             for (j = 0; j < 2; j++) {
                 if (dev->ctrl[i] & CTRL_INT_EDGE(j)) {
-                    level_status &= ~STATUS_INT(i, j);
+                    level_status &= ~TPCI200_STATUS_INT(i, j);
                 }
             }
         }
@@ -269,23 +269,23 @@ static void tpci200_write_las0(void *opaque, hwaddr addr, uint64_t val,
                 IPackDevice *ip = ipack_device_find(&s->bus, i);
 
                 if (ip != NULL) {
-                    if (val & STATUS_INT(i, 0)) {
+                    if (val & TPCI200_STATUS_INT(i, 0)) {
                         DPRINTF("Clear IP %c INT0# status\n", 'A' + i);
                         qemu_irq_lower(ip->irq[0]);
                     }
-                    if (val & STATUS_INT(i, 1)) {
+                    if (val & TPCI200_STATUS_INT(i, 1)) {
                         DPRINTF("Clear IP %c INT1# status\n", 'A' + i);
                         qemu_irq_lower(ip->irq[1]);
                     }
                 }
 
-                if (val & STATUS_TIMEOUT(i)) {
+                if (val & TPCI200_STATUS_TIMEOUT(i)) {
                     DPRINTF("Clear IP %c timeout\n", 'A' + i);
-                    s->status &= ~STATUS_TIMEOUT(i);
+                    s->status &= ~TPCI200_STATUS_TIMEOUT(i);
                 }
             }
 
-            if (val & STATUS_ERR_ANY) {
+            if (val & TPCI200_STATUS_ERR_ANY) {
                 DPRINTF("Unexpected write to STATUS register: 0x%x\n",
                         (unsigned) val);
             }
@@ -337,7 +337,7 @@ static uint64_t tpci200_read_las1(void *opaque, hwaddr addr, unsigned size)
             /* Read address 0 to ACK IP INT0# and address 2 to ACK IP INT1# */
             if (offset == 0 || offset == 2) {
                 unsigned intno = offset / 2;
-                bool int_set = s->status & STATUS_INT(ip_n, intno);
+                bool int_set = s->status & TPCI200_STATUS_INT(ip_n, intno);
                 bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno);
                 if (int_set && !int_edge_sensitive) {
                     qemu_irq_lower(ip->irq[intno]);
-- 
1.7.10.4