From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvLcm-0003FS-G9 for qemu-devel@nongnu.org; Wed, 16 Jan 2013 00:33:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TvLcl-0007z3-4o for qemu-devel@nongnu.org; Wed, 16 Jan 2013 00:33:20 -0500 Received: from cantor2.suse.de ([195.135.220.15]:59586 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TvLck-0007yi-Rv for qemu-devel@nongnu.org; Wed, 16 Jan 2013 00:33:19 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 2B044A5203 for ; Wed, 16 Jan 2013 06:33:18 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 16 Jan 2013 06:32:49 +0100 Message-Id: <1358314380-9400-5-git-send-email-afaerber@suse.de> In-Reply-To: <1358314380-9400-1-git-send-email-afaerber@suse.de> References: <1358314380-9400-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC qom-cpu 04/15] target-openrisc: Update CPU to QOM realizefn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Update the openrisc_cpu_realize() signature, hook it up to DeviceClass::realize and set realized =3D true in cpu_openrisc_init(). qapi/error.h is now included through qdev and no longer needed. Signed-off-by: Andreas F=C3=A4rber --- target-openrisc/cpu.c | 9 ++++++--- target-openrisc/cpu.h | 2 -- 2 Dateien ge=C3=A4ndert, 6 Zeilen hinzugef=C3=BCgt(+), 5 Zeilen entfernt= (-) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 56544d8..24205e3 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -62,9 +62,9 @@ static inline void set_feature(OpenRISCCPU *cpu, int fe= ature) cpu->env.cpucfgr =3D cpu->feature; } =20 -void openrisc_cpu_realize(Object *obj, Error **errp) +static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); + OpenRISCCPU *cpu =3D OPENRISC_CPU(dev); =20 qemu_init_vcpu(&cpu->env); cpu_reset(CPU(cpu)); @@ -117,6 +117,9 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) { OpenRISCCPUClass *occ =3D OPENRISC_CPU_CLASS(oc); CPUClass *cc =3D CPU_CLASS(occ); + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D openrisc_cpu_realizefn; =20 occ->parent_reset =3D cc->reset; cc->reset =3D openrisc_cpu_reset; @@ -165,7 +168,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) cpu =3D OPENRISC_CPU(object_new(cpu_model)); cpu->env.cpu_model_str =3D cpu_model; =20 - openrisc_cpu_realize(OBJECT(cpu), NULL); + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 return cpu; } diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 3beab45..a6243ea 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -33,7 +33,6 @@ struct OpenRISCCPU; #include "exec/cpu-defs.h" #include "fpu/softfloat.h" #include "qom/cpu.h" -#include "qapi/error.h" =20 #define TYPE_OPENRISC_CPU "or32-cpu" =20 @@ -340,7 +339,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOp= enRISCState *env) #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) =20 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); -void openrisc_cpu_realize(Object *obj, Error **errp); =20 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); int cpu_openrisc_exec(CPUOpenRISCState *s); --=20 1.7.10.4